Nexperia USA Inc. 74LVC1G32GV,125

Overview

74LVC1G32GV,125 from Nexperia is a single 2-input OR gate logic IC in SC-74A (SOT753) package with 5 terminals, operating from 1.65 V to 5.5 V supply, featuring Schmitt-trigger inputs for noise immunity and IOFF circuitry enabling partial power-down mode. It supports mixed-voltage translation between 3.3 V and 5 V systems and delivers ±24 mA output drive at 3.0 V.

For engineers reviewing the 74LVC1G32GV,125 datasheet, 74LVC1G32GV,125 pinout, 74LVC1G32GV,125 application, or 74LVC1G32GV,125 equivalent, this device is selected for low-power, space-constrained OR logic functions requiring robust input tolerance, rail-to-rail compatibility, and guaranteed operation across -40 °C to +125 °C industrial temperature range.

Technical Context

This CMOS logic gate implements standard positive-logic OR functionality (Y = A + B) with Schmitt-trigger inputs that accept slow-rising/falling signals without oscillation and tolerate overvoltage up to 5.5 V regardless of VCC level. Its IOFF feature actively disables outputs during power-down to prevent backflow current when VCC = 0 V.

The device complies with JEDEC standards JESD8-7 (1.65–1.95 V), JESD8-5 (2.3–2.7 V), and JESD8-B/JESD36 (2.7–3.6 V), and achieves propagation delays as low as 0.5 ns at 4.5–5.5 V while maintaining static leakage below ±1 μA across full temperature range.

Key Specifications

Pinout & Package

74LVC1G32GV,125 uses the SC-74A (SOT753) surface-mount package: plastic, 5-terminal, body size 3.0 × 1.7 × 1.3 mm, with gull-wing leads and pin 1 index located at lower-left corner below marking "V32".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input OR gate applications.

Compared with 74LVC1G32GW,125, the GV variant offers superior thermal performance in dense layouts; versus SN74LVC1G32DBVR, it provides verified IOFF protection critical for system-level power management integrity.

Availability

74LVC1G32GV,125 is available at Aetrix Electronics and suitable for industrial motor drives, USB-C peripheral designs, and low-power IoT sensor nodes requiring stable component supply, long-term lifecycle assurance, and consistent parametric performance across production batches.

Supply support for 74LVC1G32GV,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions, with manufacturing rooted in process control and automotive-grade quality systems.

The 74LVC1G32 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, designed specifically for energy-efficient, mixed-voltage digital interfacing in space-constrained industrial, computing, and consumer applications.

FAQ

Can 74LVC1G32GV,125 operate reliably at 1.65 V supply?

Yes. The device is fully characterized and guaranteed to meet all specifications-including propagation delay ≤8.0 ns, VIH ≥0.65×VCC, and VOL ≤0.45 V-at VCC = 1.65 V across -40 °C to +125 °C. Static current remains below 4 μA, making it ideal for battery-powered 1.8 V systems.

Does the IOFF feature require external biasing or control signals?

No. IOFF activates automatically when VCC = 0 V-no external enable/disable pin or voltage threshold setting is needed. Output Y transitions to high-impedance state regardless of A/B input states, and input leakage stays below ±2 μA, satisfying IEC 61000-4-2 system-level ESD immunity requirements.

What is the maximum capacitive load this OR gate can drive at 3.3 V?

At VCC = 3.3 V, the device drives up to 50 pF load capacitance while maintaining tPD ≤4.5 ns (typical) and VOL ≤0.55 V at 24 mA sink. For loads exceeding 50 pF, propagation delay increases linearly (~0.02 ns/pF), but functionality remains intact up to 100 pF with marginal timing margin.

Is the SC-74A (SOT753) package compatible with standard reflow profiles?

Yes. The SOT753 package is qualified for IPC/JEDEC J-STD-020D-compliant lead-free reflow, with peak temperature up to 260 °C for ≤30 seconds. Its 1.7 mm body width and 0.95 mm lead length ensure coplanarity <0.1 mm, enabling >99.8% first-pass yield in automated SMT lines using standard stencil apertures.