Nexperia USA Inc. 74LVC1G74GM,115

Overview

74LVC1G74GM,115 from Nexperia is a single positive-edge-triggered D-type flip-flop with asynchronous set (SD) and reset (RD) inputs, complementary Q and Q̅ outputs, 1.65 V to 5.5 V supply range, ±24 mA output drive at 3.0 V, and IOFF partial power-down protection. It functions as a synchronous storage element in digital control logic, clock-domain interfacing, and level translation between 3.3 V and 5 V systems.

For engineers reviewing the 74LVC1G74GM,115 datasheet, 74LVC1G74GM,115 pinout, 74LVC1G74GM,115 application, or 74LVC1G74GM,115 equivalent, this device is selected for low-voltage mixed-supply edge-triggered state retention where Schmitt-trigger input tolerance, JEDEC-compliant ESD robustness (HBM >2000 V), and guaranteed operation from –40 °C to +125 °C are required.

Technical Context

This flip-flop implements a master-slave D-latch architecture synchronized to the LOW-to-HIGH transition of CP. Asynchronous SD and RD override clocked behavior, forcing Q to HIGH or LOW independently of CP timing. The IOFF circuit disables outputs during power-down to prevent backflow current when VCC = 0 V.

All inputs feature Schmitt-trigger action, enabling reliable operation with slow-rising/falling signals up to 20 ns/V (at VCC = 1.65 V) or 10 ns/V (at VCC = 5.5 V). Input voltage tolerance extends to 5.5 V regardless of VCC, supporting direct interface with 5 V TTL logic while powered from 1.65 V–3.3 V rails.

Key Specifications

Pinout & Package

XQFN8 (SOT902-2) package: plastic ultra-thin quad flat no-lead, 8-terminal, body size 1.4 × 1.2 × 0.45 mm, exposed thermal pad, lead pitch 0.5 mm.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Compared with SN74LVC1G74DBVR and 74AUP1G74GM,115, the 74LVC1G74GM,115 uniquely delivers full dual-output functionality, 5.5 V input tolerance, and 200 MHz operation across 1.65–5.5 V - making it the only choice for mixed-voltage, high-speed, and space-constrained applications requiring both Q and Q̅.

Availability

74LVC1G74GM,115 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, automotive body control modules, and USB-C power delivery sequencing requiring stable component supply across extended temperature ranges and mixed-voltage environments.

Supply support for 74LVC1G74GM,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance, reliable logic, analog, and discrete components optimized for efficiency and miniaturization in industrial, automotive, and consumer applications.

The 74LVC1G74GM,115 belongs to Nexperia's LVC logic family, designed specifically for low-voltage, high-noise-immunity digital interfacing in space-constrained, thermally demanding systems requiring robust mixed-supply operation.

FAQ

Does the 74LVC1G74GM,115 support 5 V input signals while powered at 1.8 V?

Yes. All inputs are overvoltage tolerant up to 5.5 V regardless of VCC level, allowing direct connection to 5 V TTL or CMOS outputs even when VCC = 1.65 V–2.5 V. This eliminates external level-shifting circuitry in mixed-supply systems.

What is the minimum pulse width required on CP, SD, or RD inputs?

The minimum CP pulse width is 2.0 ns at VCC = 4.5–5.5 V; SD and RD require ≥2.0 ns at same VCC. At lower voltages (e.g., VCC = 1.65 V), minimum CP pulse width increases to 6.2 ns. These values ensure reliable edge detection and state capture.

How does the IOFF feature behave during partial power-down?

When VCC = 0 V, the IOFF circuit actively disables all outputs (Q and Q̅), limiting output leakage to ±2 μA. This prevents back-current flow into powered sections of the system, protecting downstream logic and enabling safe hot-swap operation.

Can the 74LVC1G74GM,115 be used in toggle mode (T-flip-flop configuration)?

Yes. By connecting Q̅ to the D input, the device operates as a divide-by-2 counter/toggle flip-flop on each CP rising edge. Setup and hold times remain valid in this configuration, and propagation delay (≤4.1 ns at VCC = 5.5 V) supports >200 MHz toggle rates.