Nexperia USA Inc. 74LVC1G80GW,125

Overview

74LVC1G80GW,125 from Nexperia is a single positive-edge-triggered D-type flip-flop in TSSOP5 (SOT353-1) package, operating from 1.65 V to 5.5 V supply. It stores data on the LOW-to-HIGH clock transition with 0.5 ns minimum setup time at 5 V, ±24 mA output drive at 3.0 V, and IOFF-enabled partial power-down protection. It serves as a level-translating storage element in mixed-voltage digital control paths such as microcontroller I/O expansion and sensor interface synchronization.

For engineers reviewing the 74LVC1G80GW,125 datasheet, 74LVC1G80GW,125 pinout, 74LVC1G80GW,125 application, or 74LVC1G80GW,125 equivalent, this page delivers verified functional behavior, validated timing margins across voltage ranges, confirmed TSSOP5 pin mapping, and real-world use cases in voltage-translation and edge-sensitive sampling circuits - all grounded in Nexperia's Rev. 17 product data sheet.

Technical Context

This device implements a synchronous edge-triggered storage cell with Schmitt-trigger inputs for noise immunity and robust signal acquisition from slow-rising sources. Its IOFF circuit actively disables outputs during power-down, preventing backflow current when VCC = 0 V while inputs/outputs tolerate up to 5.5 V.

It supports dual-voltage interfacing: inputs accept 3.3 V or 5 V logic levels regardless of VCC, enabling direct connection between legacy 5 V peripherals and modern 1.8 V/2.5 V controllers. Propagation delay ranges from 0.5 ns (VCC = 5 V) to 13.0 ns (VCC = 1.65 V, -40 °C to +125 °C), with guaranteed set-up/hold timing across the full industrial temperature range.

Key Specifications

Pinout & Package

TSSOP5 (SOT353-1) package: plastic thin shrink small outline, 5-lead, 1.25 mm body width, 0.65 mm pitch, 1.3 mm height. Pin 1 index located below marking "VT" in lower-left corner.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar D-type flip-flop applications.

Compared with SN74LVC1G74DBVR and 74AUP1G80GW,125, the 74LVC1G80GW,125 uniquely combines 5.5 V overvoltage tolerance, IOFF protection, and full -40 °C to +125 °C operation - making it the sole choice for robust mixed-voltage control in automotive and industrial settings.

Availability

74LVC1G80GW,125 is available at Aetrix Electronics and suitable for industrial motor control, automotive body electronics, IoT sensor hubs, and programmable logic interface applications requiring stable component supply across extended temperature and voltage ranges.

Supply support for 74LVC1G80GW,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LVC1G80 belongs to Nexperia's LVC logic family - engineered for low-voltage, high-noise-immunity digital interfacing in space-constrained, thermally demanding applications where reliability across voltage and temperature extremes is critical.

FAQ

Does 74LVC1G80GW,125 support 5 V input signals when powered from 1.8 V?

Yes. Its inputs are overvoltage tolerant up to 5.5 V regardless of VCC level, allowing direct connection of 5 V sensors or legacy peripherals to a 1.8 V system without external level-shifting components. This is confirmed in Table 6 (Recommended Operating Conditions) and Section 2 (Features and benefits) of the Rev. 17 datasheet.

What is the maximum clock frequency supported at 2.5 V supply?

At VCC = 2.5 V (within 2.3 V–2.7 V range), the maximum clock frequency is 160 MHz minimum and 350 MHz typical per Table 8. This is validated across -40 °C to +125 °C ambient, with pulse width tW ≥ 2.5 ns required for reliable operation.

How does the IOFF feature behave during power-down?

When VCC = 0 V, the IOFF circuitry forces Q output into a high-impedance state with leakage ≤ ±2 μA (Table 7), blocking reverse current flow from other powered rails. This behavior is active without external control and is specified for all temperatures from -40 °C to +125 °C.

Is the TSSOP5 package RoHS-compliant and lead-free?

Yes. The 74LVC1G80GW,125 in SOT353-1 package is manufactured using lead-free solderable terminations and complies with EU RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006, as documented in Nexperia's official compliance statements and material declarations.