NXP Semiconductors 74LVC1G86GM,132

Overview

74LVC1G86GM,132 from Nexperia is a single 2-input EXCLUSIVE-OR gate in XSON6 (SOT886) package, operating from 1.65 V to 5.5 V supply, with ±24 mA output drive at 3.0 V, IOFF-enabled partial power-down protection, and -40 °C to +125 °C temperature rating-used for logic-level translation and signal conditioning in space-constrained industrial control interfaces.

For engineers reviewing the 74LVC1G86GM,132 datasheet, 74LVC1G86GM,132 pinout, 74LVC1G86GM,132 application, or 74LVC1G86GM,132 equivalent, key selection criteria include mixed-voltage interface capability (3.3 V/5 V tolerant inputs), IOFF-backed power sequencing safety, propagation delay ≤6.5 ns at 3.3 V, overvoltage-tolerant inputs up to 5.5 V, and thermal performance in XSON6's 1.0 × 1.45 × 0.5 mm body.

Technical Context

This device implements a CMOS-based XOR logic function with symmetrical input structure, enabling bidirectional voltage-level translation between 1.65 V and 5.5 V domains without external biasing. Its IOFF circuit actively disables outputs during VCC = 0 V, blocking backflow current in hot-swap or partial-power-down systems.

The XSON6 (SOT886) package features six terminals-including two inputs (A, B), one output (Y), VCC, GND, and one no-connect terminal-with exposed die pad not electrically connected. Input thresholds scale with VCC (e.g., VIH = 0.7VCC at 4.5–5.5 V), ensuring TTL-compatible operation across supply ranges.

Key Specifications

Pinout & Package

XSON6 (SOT886) package: plastic extremely thin small outline, no leads, 6 terminals, body dimensions 1.0 mm × 1.45 mm × 0.5 mm, thermal pad not connected.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 2-input XOR gate applications.

Compared with SN74LVC1G86DBVR and 74AUP1G86GW,125, the 74LVC1G86GM,132 uniquely balances 5 V input tolerance, XSON6 space efficiency, and IOFF safety-making it the sole option for compact, mixed-supply, hot-pluggable designs requiring guaranteed back-current blocking.

Availability

74LVC1G86GM,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, USB-C power delivery subsystems, automotive body control modules, and IoT edge node wake-up logic requiring stable component supply across extended temperature and mixed-voltage environments.

Supply support for 74LVC1G86GM,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions with focus on reliability, efficiency, and miniaturization for industrial, automotive, and consumer markets.

The 74LVC1G86 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family-designed specifically for robust, low-power, mixed-voltage digital interfacing in space- and power-constrained applications.

FAQ

Can 74LVC1G86GM,132 operate with VCC = 1.65 V while receiving 3.3 V input signals?

Yes. Inputs are overvoltage tolerant up to 5.5 V independent of VCC level. At VCC = 1.65 V, VIH is guaranteed ≥0.65×VCC (≥1.07 V), and 3.3 V input exceeds this by >200%, ensuring reliable HIGH recognition without damage or excessive leakage.

What is the function of the n.c. pin in the XSON6 package?

Pin 5 is internally unconnected. It may be left floating or tied to GND to improve mechanical stability and reduce solder voiding during reflow. No electrical function is assigned-no current flows, and it does not affect timing, noise immunity, or power consumption.

Does IOFF protect against back-current when VCC is partially ramped (e.g., 0.5 V)?

No. IOFF activates only when VCC = 0 V. At intermediate voltages (e.g., 0.5 V), standard CMOS leakage paths remain active. For partial-ramp protection, external series FETs or diodes are required-the IOFF feature is strictly for full power-down scenarios.

How does propagation delay vary across temperature and voltage?

At VCC = 3.0 V, tpd is 2.3 ns (typ) at 25 °C and increases to 6.5 ns (max) at +125 °C. At VCC = 1.65 V, max tpd rises to 13.0 ns at +125 °C. All values are specified across -40 °C to +125 °C per JEDEC JESD8-7, with no derating required below 74 °C.