Diodes Incorporated 74LVC1G97DW-7
- Part No.:
- 74LVC1G97DW-7
- Manufacturer:
- Diodes Incorporated
- Package:
- 6-TSSOP, SC-88, SOT-363
- Datasheet:
-
74LVC1G97DW-7.pdf
- Description:
- IC CONFIG MULT-FUNC GATE SOT363
- Quantity:
- Payment:

- Shipping:

Inventory:113,732
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Product details
Overview
74LVC1G97DW-7 from Diodes Incorporated is a single three-input configurable multiple-function logic gate in SOT363 package, supporting MUX, AND, OR, NAND, NOR, inverter, and non-inverting buffer functions via 3-bit input pattern selection. It operates from 1.65V to 5.5V, delivers ±24mA output drive at 3.3V, features 5.5V-tolerant inputs, and includes IOFF circuitry for partial power-down protection. Used in voltage-level shifting and power-down signal isolation in portable consumer electronics.
For engineers reviewing the 74LVC1G97DW-7 datasheet, 74LVC1G97DW-7 pinout, 74LVC1G97DW-7 application, or 74LVC1G97DW-7 equivalent, this page provides verified functional configurations, Schmitt-trigger input behavior implications, IOFF leakage specs, thermal resistance (θJA = 371°C/W), and real-world logic reconfiguration use cases-not generic logic gate summaries.
Technical Context
The device implements a fixed 3-input combinational lookup table with eight possible output states determined by IN2/IN1/IN0, enabling user-selectable logic functions without external programming. Its Schmitt-trigger inputs provide hysteresis (ΔVT = 0.32–1.40V depending on VCC), improving noise immunity in noisy digital environments.
IOFF circuitry actively disables the output when VCC = 0V, limiting backflow current to ±2μA even with 5.5V applied to I/O pins-critical for mixed-voltage system power sequencing. Propagation delay ranges from 0.7ns (min) to 18.0ns (max) across temperature and supply conditions, with CL = 30–50pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65V to 5.5V - Enables direct interface with 1.8V, 2.5V, 3.3V, and 5V logic domains. |
| Input Voltage Tolerance | Up to 5.5V - Allows safe connection to higher-voltage signals without level shifters. |
| Output Drive Strength | ±24mA at VCC = 3V - Sufficient to drive moderate capacitive loads or fan-out to multiple CMOS inputs. |
| IOFF Leakage Current | ±2μA max - Prevents damaging back-current during partial power-down in multi-rail systems. |
| Propagation Delay (tpd) | 0.7ns (min) to 18.0ns (max) - Supports timing-critical paths up to ~55MHz in best-case conditions. |
| Input Hysteresis (ΔVT) | 0.32V to 1.40V - Reduces susceptibility to noise-induced glitches on slow or noisy input edges. |
| Power Consumption (ICC) | 4μA max - Enables ultra-low static power in battery-powered standby modes. |
Pinout & Package
SOT363 package: 6-pin compact surface-mount package with exposed pad option (not thermally enhanced per datasheet), footprint dimensions 2.15mm × 2.10mm × 0.95mm (D × E × A2), moisture sensitivity level 1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | IN1 | Primary data input; part of 3-bit configuration word determining logic function. |
| 2 | GND | Ground reference for internal circuitry and output stage; must be low-impedance. |
| 3 | IN0 | Secondary data input; combined with IN1 and IN2 to select one of eight logic outputs. |
| 4 | Y | Push-pull CMOS output; actively driven high/low; supports bus-hold if externally biased. |
| 5 | VCC | Positive supply rail; powers internal logic and output stage; IOFF active when VCC = 0V. |
| 6 | IN2 | Tertiary data input; MSB of 3-bit configuration code; determines truth table mapping. |
Key Features
| Feature | Design Value |
|---|---|
| Configurable Logic Function | Eight selectable functions (MUX, AND, OR, NAND, NOR, inverter, buffer) via static 3-bit input coding-no configuration register or clock required. |
| 5.5V-Tolerant Inputs | Accepts 5.5V signals while powered from as low as 1.65V-enables seamless level translation without external components. |
| IOFF Partial Power-Down | Automatically disables output to high-impedance state with <±2μA leakage when VCC = 0V-prevents backfeeding in hot-swap or multi-rail sequencing. |
| Schmitt-Trigger Inputs | Hysteresis range 0.32–1.40V improves noise margin on slow-rise/fall signals and eliminates contact bounce artifacts. |
| Low Dynamic Power | 23pF typical power dissipation capacitance at 3.3V/10MHz-reduces switching current and EMI in high-frequency routing. |
Applications
| USB-C Port Controller Signal Routing | Industrial PLC Digital Input Conditioning |
|---|---|
Use Scenario: Isolating and translating control signals between 5V legacy sensors and 3.3V microcontroller I/O in USB-C port controller subsystems. IC Role / Device Role / Timing Role: Configured as a 2-to-1 multiplexer to route either VBUS detection or CC line status to MCU GPIO, with IOFF preventing backfeed during port reset. Use Value: Eliminates need for discrete level shifters and enables dynamic reconfiguration via firmware-controlled input patterns. | Use Scenario: Debouncing and noise filtering of mechanical switch inputs in programmable logic controller (PLC) digital input modules operating in electrically noisy factory environments. IC Role / Device Role / Timing Role: Configured as an inverter with Schmitt-trigger inputs to clean switch bounce and EMI transients before latching into FPGA logic. Use Value: Achieves >1.2V hysteresis at 24V-derived 3.3V rail, reducing false triggers without external RC networks or software polling. |
| Wearable Device Power Sequencing | Automotive Infotainment Display Interface |
Use Scenario: Managing enable/disable sequencing of RF transceiver and sensor subsystems during sleep/wake transitions in battery-constrained wearables. IC Role / Device Role / Timing Role: Configured as a NOR gate to combine wake-on-motion and wake-on-button signals, with IOFF ensuring zero current draw when main PMIC is off. Use Value: Guarantees <2μA leakage during deep sleep-extending battery life beyond 7 days on coin-cell power. | Use Scenario: Level-shifting and signal conditioning between 5V display timing controller and 1.8V MIPI D-PHY receiver in automotive infotainment head units. IC Role / Device Role / Timing Role: Configured as a non-inverting buffer with 5.5V-tolerant inputs to accept 5V sync pulses while driving 1.8V logic thresholds. Use Value: Maintains <6.4ns max propagation delay across -40°C to +125°C, preserving pixel clock integrity under thermal stress. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G97DBVR | SOT23-6 package; θJA = 204°C/W; no Schmitt inputs; identical logic function set and IOFF spec. | Better thermal performance but lacks input hysteresis-requires external filtering in noisy environments. | Select when board space allows larger SOT23-6 and system noise floor is low. |
| 74LVC1G98GW,125 | Same SOT363 package; includes dual independent 3-input configurable gates; higher ICC (8μA max). | Doubles logic density but increases static current-unsuitable for ultra-low-power always-on nodes. | Select when two independent configurable functions are needed per footprint and 4μA budget can be relaxed. |
Compared with SN74LVC1G97DBVR, the 74LVC1G97DW-7 trades thermal advantage for robust noise immunity via Schmitt inputs; compared with 74LVC1G98GW,125, it halves static current at the cost of logic density-making it optimal for single-function, battery-sensitive designs.
Availability
74LVC1G97DW-7 is available at Aetrix Electronics and suitable for voltage-level shifting, power-down signal isolation, and general-purpose logic reconfiguration requiring stable component supply across consumer, industrial, and automotive design cycles.
Supply support for 74LVC1G97DW-7 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Diodes Incorporated is a global semiconductor company specializing in discrete, analog, and logic solutions, with design centers in Asia, Europe, and the U.S., and manufacturing in ISO/TS 16949-certified facilities.
The 74LVC logic family targets low-voltage, mixed-supply digital interfacing applications-designed for interoperability across 1.65V–5.5V domains while maintaining industry-standard speed/power trade-offs.
FAQ
What logic functions does the 74LVC1G97DW-7 support, and how are they selected?
The device supports eight logic functions: 2-to-1 MUX, 2-input AND, OR, NAND, NOR (with one or both inputs inverted), inverter, and non-inverting buffer. Selection is achieved by applying specific high/low voltage combinations to the three inputs (IN2, IN1, IN0) per the Function Table-no external programming or clocking is required.
Does the 74LVC1G97DW-7 require external pull-up or pull-down resistors on unused inputs?
Yes. Per datasheet Note 6, unused inputs must be tied to VCC or GND to prevent floating states that increase ICC and risk metastability. The device does not include internal weak pull-ups/pull-downs, and leaving inputs unconnected may cause excessive current draw or erratic output behavior.
Can the 74LVC1G97DW-7 be used in a 5V-only system without level shifting?
No-it requires a minimum VCC of 1.65V but cannot operate with VCC = 0V while inputs are at 5V. However, its 5.5V-tolerant inputs allow it to accept 5V signals when powered from 3.3V or 2.5V rails, making it ideal for level translation from higher-voltage peripherals to lower-voltage controllers.
How does the Schmitt-trigger input affect timing analysis in synchronous designs?
Schmitt-trigger inputs introduce asymmetric threshold voltages (VT+ and VT−), increasing effective input rise/fall time but eliminating noise-induced glitches. For timing-critical paths, designers must account for worst-case tpd (18.0ns at −40°C to +125°C) and ensure input slew rates meet minimum 2ns/V requirement per test condition-especially when driving from slow microcontroller GPIOs.
74LVC1G97DW-7 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Diodes Incorporated
- Series:
- 74LVC
- Package/Case:
- 6-TSSOP, SC-88, SOT-363
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-363
74LVC1G97DW-7 FAQ
1.How can I place an order for 74LVC1G97DW-7 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC1G97DW-7 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC1G97DW-7 reliable?
The price and inventory of 74LVC1G97DW-7 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC1G97DW-7 is usually 5 days.
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Once your 74LVC1G97DW-7 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC1G97DW-7?
For technical support, including 74LVC1G97DW-7 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC1G97DW-7 requirements.
6.How does Aetrix verify that 74LVC1G97DW-7 is sourced from the original manufacturer or authorized distributors?
All 74LVC1G97DW-7 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC1G97DW-7 meets industry standards.
7.What is the process for return or replacement of 74LVC1G97DW-7?
All 74LVC1G97DW-7 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC1G97DW-7, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC1G97DW-7 part is unused and in its original packaging.
Return procedure for 74LVC1G97DW-7:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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