NXP Semiconductors 74LVC1G97GN,132
- Part No.:
- 74LVC1G97GN,132
- Manufacturer:
- NXP Semiconductors
- Package:
- 6-XFDFN
- Datasheet:
-
74LVC1G97GN,132.pdf
- Description:
- LOGIC CIRCUIT, CMOS, PDSO6
- Quantity:
- Payment:

- Shipping:

Inventory:15,000
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Product details
Overview
74LVC1G97GN,132 from Nexperia is a single-gate configurable logic device with Schmitt-trigger inputs, supporting MUX, AND, OR, NAND, NOR, inverter, and buffer functions via 3-bit configuration. It operates from 1.65 V to 5.5 V, tolerates 5 V inputs/outputs, and features IOFF power-down protection. Used in mixed-voltage signal conditioning and level translation between 3.3 V and 5 V subsystems in industrial control I/O modules.
For engineers reviewing the 74LVC1G97GN,132 datasheet, 74LVC1G97GN,132 pinout, 74LVC1G97GN,132 application, or 74LVC1G97GN,132 equivalent, this device serves as a space-constrained, low-power logic reconfiguration element where voltage translation, noise immunity, and partial power-down capability are critical selection criteria.
Technical Context
The 74LVC1G97GN implements a single configurable gate using CMOS logic with Schmitt-trigger inputs for enhanced noise rejection. Its function is determined by the logic states of its three data inputs (A, B, C), enabling dynamic reconfiguration without external programming hardware.
It supports true bidirectional voltage translation: inputs accept 0–5.5 V regardless of VCC (1.65–5.5 V), and outputs drive compliant loads at VCC levels. The IOFF circuit actively disables outputs during power-down, blocking backflow current when VCC = 0 V.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 5.5 V - Enables operation across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains. |
| Input Voltage Tolerance | 0 V to 5.5 V - Allows direct interface with 5 V TTL/CMOS drivers while powered from lower VCC. |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - Sufficient to drive standard CMOS loads and small capacitive buses. |
| Propagation Delay | 0.5 ns to 7.9 ns - Varies with VCC; 3.8 ns typical at 3.3 V, enabling use in sub-100 MHz timing paths. |
| Hysteresis Voltage | 0.50 V typical at VCC = 3.0 V - Provides >300 mV noise margin for slow or noisy input signals. |
| IOFF Leakage | ±2 μA max at VCC = 0 V - Prevents disruptive current flow in hot-swap or partial-power-down systems. |
| Operating Temperature | −40 °C to +125 °C - Qualified for under-hood, industrial, and extended-temperature embedded applications. |
Pinout & Package
XSON6 package (SOT1115): extremely thin small outline, no leads, 6-terminal surface-mount package measuring 0.9 mm × 1.0 mm × 0.35 mm, optimized for high-density PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A | Data input | Primary logic input used in all function configurations; Schmitt-triggered for noise immunity. |
| B | Data input | Secondary logic input; combined with A and C to select gate function and routing path. |
| C | Data input | Configuration input determining logic mode (e.g., C=H selects inverter/buffer; C=L enables MUX/AND/OR). |
| Y | Data output | Single buffered output reflecting configured logic result; supports rail-to-rail swing. |
| VCC | Power supply | Core supply pin; powers internal logic and output stage; IOFF active when VCC = 0 V. |
| GND | Ground reference | 0 V reference for all input thresholds, output levels, and internal biasing. |
Key Features
| Feature | Design Value |
|---|---|
| Configurable logic function | One device replaces seven discrete gates (MUX, AND, OR, NAND, NOR, inverter, buffer) via input-state encoding. |
| 5 V tolerant I/O | Inputs and outputs operate safely with 5 V signals while VCC is as low as 1.65 V-enables seamless 3.3 V ↔ 5 V bridging. |
| Schmitt-trigger inputs | Hysteresis ≥0.44 V at VCC = 3.0 V improves noise immunity on slow-rising or electrically noisy control lines. |
| IOFF partial power-down | Output high-impedance state activated automatically when VCC = 0 V, eliminating backfeed risk in live-backplane systems. |
| Ultra-small XSON6 footprint | 0.9 mm × 1.0 mm body area saves >60% board space vs. TSSOP6, critical for wearables and compact IoT nodes. |
Applications
| Industrial Sensor Interface | USB-C Power Delivery Control |
|---|---|
Use Scenario: Conditioning analog sensor enable signals and digital status flags in factory-floor PLC I/O modules exposed to EMI. IC Role / Device Role / Timing Role: Configured as Schmitt-trigger buffer to clean up slow-rising thermocouple alarm lines before MCU sampling. Use Value: 0.5 V hysteresis rejects >200 mV of coupled noise; 5 V tolerance allows direct connection to legacy 5 V sensor outputs. | Use Scenario: Managing CC line logic states and VCONN enable sequencing in USB-C port controllers. IC Role / Device Role / Timing Role: Configured as NAND gate to combine VBUS presence and policy engine command for VCONN power switch control. Use Value: Sub-5 ns propagation delay ensures timing compliance with USB PD 3.1 specification; IOFF prevents leakage during port reset. |
| Automotive Body Control Module | Low-Power Wearable Button Debounce |
Use Scenario: Interfacing mechanical door latch switches and LED driver enable lines in 12 V vehicle subsystems. IC Role / Device Role / Timing Role: Configured as OR gate with one inverted input to detect any latch-open event across four doors. Use Value: −40 °C to +125 °C rating meets automotive under-hood requirements; 1.65 V min VCC supports battery brownout operation. | Use Scenario: Debouncing tactile buttons in hearables and smart patches where PCB area and quiescent current are constrained. IC Role / Device Role / Timing Role: Configured as inverter with Schmitt input to eliminate contact bounce without external RC network. Use Value: 0.1 μA typical ICC at 3.3 V extends battery life; 0.9 mm × 1.0 mm XSON6 fits beneath 2 mm button domes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar configurable logic gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC1G57GW,125 | Same logic architecture and pinout, but in TSSOP6 (SOT363-2) package - 2.2 mm × 1.35 mm body, 0.65 mm pitch. | Higher profile and larger footprint; better suited for manual assembly or prototyping where XSON6 rework is impractical. | Select when board-level rework capability, thermal mass for soldering, or legacy footprint compatibility is required. |
| SN74LVC1G97DBVR | TI variant in SOT-23-6 (DBV) package - 2.9 mm × 1.6 mm, 0.95 mm pitch; identical electrical specs but different marking and qualification. | Not qualified to AEC-Q100; lacks Nexperia's extended −40 °C to +125 °C guarantee across full voltage range. | Select only for non-automotive commercial designs where TI supply chain preference or DBV footprint reuse drives choice. |
Compared with 74LVC1G57GW,132 and SN74LVC1G97DBVR, the 74LVC1G97GN,132 offers the smallest PCB footprint and guaranteed operation across the full industrial temperature range with IOFF - making it optimal for miniaturized, thermally demanding, or hot-swap-capable systems.
Availability
74LVC1G97GN,132 is available at Aetrix Electronics and suitable for industrial sensor interfaces, USB-C power delivery subsystems, and automotive body control modules requiring stable component supply and long-term manufacturability.
Supply support for 74LVC1G97GN,132 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a leading semiconductor manufacturer specializing in high-performance, energy-efficient logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74LVC1G97 belongs to Nexperia's LVC low-voltage CMOS logic family, designed specifically for voltage translation, signal conditioning, and logic flexibility in space-constrained, mixed-supply embedded systems.
FAQ
What logic functions can the 74LVC1G97GN,132 configure, and how is configuration performed?
The 74LVC1G97GN,132 can be configured as a 2-input MUX, AND, OR, NAND, NOR, inverter, or buffer by setting the logic states of its three inputs (A, B, C). Configuration is static and determined solely by the DC voltage levels applied to those pins at power-up or runtime - no clock, programming interface, or external memory is required. The function table in section 7.1 of the datasheet defines exact input combinations.
Does the 74LVC1G97GN,132 support true bidirectional level shifting between 3.3 V and 5 V domains?
No - it supports unidirectional voltage translation only. Inputs tolerate 0–5.5 V regardless of VCC, allowing 5 V signals to drive the device when powered from 3.3 V. However, the output swings between GND and VCC, so a 3.3 V-powered device cannot produce a 5 V output. For true bidirectional shifting, a dedicated level translator IC is required.
How does the IOFF feature protect the device during partial power-down?
When VCC is at 0 V, the IOFF circuit forces the output (Y) into a high-impedance state and blocks current flow through the input/output structures. This prevents damaging backflow current from externally driven inputs or outputs into the unpowered device - a critical safeguard in systems with live backplanes, hot-pluggable modules, or staggered power sequencing.
Can the 74LVC1G97GN,132 be used in automotive applications, and what qualifications does it hold?
The 74LVC1G97GN,132 is specified for −40 °C to +125 °C operation and built on Nexperia's qualified automotive-grade process, but it is not officially AEC-Q100 qualified. It is widely used in non-safety-critical automotive body electronics (e.g., lighting controls, door modules) where customers perform their own validation. For ASIL-B or higher systems, an AEC-Q100-qualified alternative must be selected.
74LVC1G97GN,132 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- 74LVC
- Package/Case:
- 6-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Configurable Multiple Function
- Number of Circuits:
- 1
- Number of Inputs:
- 3
- Schmitt Trigger Input:
- No
- Output Type:
- Single-Ended
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-XSON (0.9x1)
74LVC1G97GN,132 FAQ
1.How can I place an order for 74LVC1G97GN,132 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC1G97GN,132 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC1G97GN,132 reliable?
The price and inventory of 74LVC1G97GN,132 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC1G97GN,132 is usually 5 days.
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5.How can I obtain technical support or documentation for 74LVC1G97GN,132?
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6.How does Aetrix verify that 74LVC1G97GN,132 is sourced from the original manufacturer or authorized distributors?
All 74LVC1G97GN,132 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC1G97GN,132 meets industry standards.
7.What is the process for return or replacement of 74LVC1G97GN,132?
All 74LVC1G97GN,132 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC1G97GN,132, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC1G97GN,132 part is unused and in its original packaging.
Return procedure for 74LVC1G97GN,132:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC1G97GN,132 Tags

-
SN74LVC1G97DCKR
Texas Instruments

-
SN74LVC1G97DRLR
Texas Instruments

-
SN74LVC1G97DBVR
Texas Instruments

-
NC7SZ57P6X
onsemi

-
SN74LVC1G97DCKT
Texas Instruments

-
MC100EP05DTR2G
onsemi

-
MC100EP08DTR2G
onsemi

-
NB7L86AMNHTBG
onsemi

-
HMC722LP3E
Analog Devices Inc.

-
74LVC1G97GW,125
Nexperia USA Inc.

-
74LVC1G57GW,125
Nexperia USA Inc.

-
74LVC1G97GV,125
Nexperia USA Inc.
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