Nexperia USA Inc. 74LVC2G02DP,125
- Part No.:
- 74LVC2G02DP,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
74LVC2G02DP,125.pdf
- Description:
- IC GATE NOR 2CH 2-INP 8TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LVC2G02DP,125 from Nexperia is a dual 2-input NOR gate logic IC in TSSOP8 (SOT505-2) package, operating from 1.65 V to 5.5 V supply, featuring 5 V-tolerant inputs/outputs, ±24 mA output drive at 3.0 V, IOFF partial power-down protection, and Schmitt-trigger inputs for noise immunity in mixed-voltage digital interfaces.
For engineers reviewing the 74LVC2G02DP,125 datasheet, 74LVC2G02DP,125 pinout, 74LVC2G02DP,125 application, or 74LVC2G02DP,125 equivalent, this device serves as a voltage-translating logic gate in level-shifting I/O buffers, reset signal conditioning, and enable control circuits where robustness against slow edges and power sequencing is required.
Technical Context
This device implements two independent CMOS NOR gates with rail-to-rail input voltage tolerance up to 5.5 V and guaranteed operation down to 1.65 V. Each gate features Schmitt-trigger inputs with hysteresis, enabling reliable switching despite slow or noisy input transitions.
The IOFF circuit actively disables outputs when VCC = 0 V, blocking backflow current during partial power-down-critical for hot-swap and multi-rail system designs. Propagation delay ranges from 0.6 ns (at 5 V) to 11.2 ns (at 1.65 V, –40 °C to +125 °C), supporting both high-speed and ultra-low-voltage operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 5.5 V - Enables direct interface between 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains without external level shifters. |
| Input Voltage Tolerance | Up to 5.5 V - Inputs remain functional and non-damaging even when driven by 5 V signals while VCC is at 1.65–3.3 V. |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - Sufficient to directly drive multiple standard CMOS/TTL loads or small capacitive buses. |
| IOFF Leakage Current | ±2 μA max at VCC = 0 V - Ensures negligible current flow through powered-down device, preventing bus contention or unintended biasing. |
| Propagation Delay | 0.6 ns (min) to 11.2 ns (max) - Supports timing-critical combinational logic paths across industrial temperature range (–40 °C to +125 °C). |
| Operating Temperature | –40 °C to +125 °C - Qualified for under-hood automotive auxiliary modules, industrial PLC I/O, and extended-temperature embedded controllers. |
| ESD Protection | HBM >2000 V, CDM >1000 V - Robust handling during board assembly and field service without additional protection circuitry. |
Pinout & Package
TSSOP8 package (SOT505-2): plastic thin shrink small outline, 8 leads, 3 mm body width, 0.5 mm lead length, 0.65 mm pitch, exposed pad not present.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | First NOR gate input A - Accepts 0–5.5 V logic signals; Schmitt-triggered for noise margin and edge-rate tolerance. |
| 2 | VCC | Positive supply - Powers both gates; must be decoupled locally due to fast switching transients. |
| 3 | 1B | First NOR gate input B - Electrically identical to Pin 1; dual-input NOR function requires both A and B low for high output. |
| 4 | 1Y | First NOR gate output - Active-low logic: Y = NOT(A OR B); drives loads up to ±24 mA at 3.0 V. |
| 5 | 2Y | Second NOR gate output - Independent of first gate; shares no internal resources; supports asynchronous logic paths. |
| 6 | 2B | Second NOR gate input B - Fully isolated from Pin 3; enables independent dual-gate implementation. |
| 7 | GND | Ground reference - Must be low-impedance return path for both supply and output currents; shared with VCC decoupling. |
| 8 | 2A | Second NOR gate input A - Matches Pin 1 electrically; pin numbering follows JEDEC-standard TSSOP8 layout (Pin 1 index bottom-left). |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent NOR gates | Two fully isolated logic functions in one 8-pin package - reduces board space vs. discrete gates or larger logic arrays. |
| Schmitt-trigger inputs | Hysteresis on all four inputs - eliminates chatter on slow-rising reset or enable lines; eliminates need for external RC filtering. |
| IOFF partial power-down | Outputs disabled with leakage < ±2 μA when VCC = 0 V - prevents backfeed in multi-supply systems during sequencing or fault conditions. |
| 5 V tolerant I/O | Inputs and outputs withstand 5.5 V regardless of VCC (1.65–5.5 V) - enables seamless interfacing with legacy 5 V peripherals without translators. |
| Wide temperature range | Specified from –40 °C to +125 °C - supports deployment in engine control units, motor drives, and outdoor industrial equipment. |
Applications
| Industrial Sensor Interface | Power Sequencing Control |
|---|---|
|
Use Scenario: Combining multiple sensor fault signals (e.g., overtemperature, overcurrent) into a single hardware shutdown line. IC Role / Device Role / Timing Role: Dual NOR gate performs wired-OR logic inversion: any active-high fault forces output low to trigger system disable. Use Value: Eliminates need for external pull-up resistors or discrete transistors; Schmitt inputs reject EMI-induced glitches on long sensor traces. |
Use Scenario: Enabling downstream regulators only after primary rail stabilizes, using delayed reset and power-good signals. IC Role / Device Role / Timing Role: One NOR gate combines delayed reset and PG# to generate controlled enable; second gate provides inverted status feedback. Use Value: IOFF ensures no current flows into the gate when main VCC is off, preserving isolation between power domains during startup/shutdown. |
| USB-C Port Power Negotiation | Legacy Microcontroller GPIO Expansion |
|
Use Scenario: Translating 5 V USB PD controller signals to 3.3 V microcontroller inputs while maintaining noise immunity. IC Role / Device Role / Timing Role: Level-shifting NOR gate acts as bidirectional signal conditioner for CC line status monitoring. Use Value: 5 V-tolerant inputs accept PD controller outputs directly; Schmitt action rejects coupling noise from high-speed USB data lines. |
Use Scenario: Adding two extra active-low enable outputs to an MCU with limited GPIO, driving LED indicators or peripheral resets. IC Role / Device Role / Timing Role: NOR gate configured as inverter (one input tied low) provides clean, high-drive active-low outputs. Use Value: ±24 mA drive capability allows direct LED driving without series resistors; low ICC (<4 μA) minimizes standby power impact. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual NOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G02DCKR | Same logic function, VSSOP8 (SOT765-1) package; 2.3 mm body width; slightly higher thermal resistance than TSSOP8. | Preferred for ultra-dense PCB layouts where 0.7 mm narrower footprint is critical; same electrical specs and temperature range. | Select when board space is constrained and thermal load is moderate; verify solder paste volume for fine-pitch VSSOP reflow. |
| 74LVC2G02GT,115 | XSON8 (SOT833-1) package: 1.0 × 1.95 × 0.5 mm, no leads, 0.5 mm pitch; lower parasitic inductance but requires precise stencil design. | Optimized for high-frequency signal integrity and minimal board area in portable electronics; not suitable for manual prototyping. | Choose for mass-produced consumer devices where size and EMI performance outweigh assembly complexity. |
Compared with SN74LVC2G02DCKR and 74LVC2G02GT,115, the 74LVC2G02DP,125 offers the best balance of thermal performance, manufacturability, and compatibility with standard TSSOP reflow profiles-making it ideal for industrial and automotive-adjacent designs requiring reliability and process robustness.
Availability
74LVC2G02DP,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, power sequencing control, USB-C port management, and microcontroller GPIO expansion requiring stable component supply across extended temperature and mixed-voltage environments.
Supply support for 74LVC2G02DP,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for automotive, industrial, and consumer markets.
The 74LVC2G02 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, designed specifically for robust voltage translation and noise-immune digital interfacing in multi-rail embedded systems.
FAQ
Can 74LVC2G02DP,125 operate with VCC = 1.8 V while accepting 3.3 V inputs?
Yes. The device is fully specified from 1.65 V to 5.5 V supply and supports overvoltage-tolerant inputs up to 5.5 V. At VCC = 1.8 V, VIH is 0.65 × VCC ≈ 1.17 V and VIL is 0.35 × VCC ≈ 0.63 V, ensuring reliable recognition of 3.3 V logic levels as HIGH without damage or undefined behavior.
Does the IOFF feature work when only one supply rail is powered down?
Yes. IOFF activates whenever VCC = 0 V, regardless of input/output voltage states. With VCC unpowered, outputs are high-impedance and leakage remains ≤±2 μA-even if 5 V signals are applied to inputs or outputs-preventing back-current paths in partial-power-down scenarios.
What is the maximum capacitive load this device can drive at 10 MHz?
Based on CPD = 14 pF per gate and dynamic power formula PD = CPD × VCC² × fi × N, at VCC = 3.3 V and fi = 10 MHz, dynamic dissipation is ~1.5 mW per gate. With typical PCB trace capacitance < 5 pF and recommended CL ≤ 50 pF, the device reliably drives loads up to 30–40 pF at 10 MHz without exceeding thermal limits in TSSOP8.
Is the 74LVC2G02DP,125 qualified for automotive applications?
No. While rated for –40 °C to +125 °C, this variant is not AEC-Q100 qualified and lacks automotive-specific testing (e.g., HTOL, ESD stress beyond HBM 2 kV). Nexperia offers automotive-grade equivalents (e.g., 74LVC2G02DP/AU) with full qualification-this part is intended for industrial, computing, and consumer use.
74LVC2G02DP,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- NOR Gate
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 4 µA
- Current - Output High, Low:
- 32mA, 32mA
- Input Logic Level - Low:
- 0.7V ~ 0.8V
- Input Logic Level - High:
- 1.7V ~ 2V
- Max Propagation Delay @ V, Max CL:
- 4.3ns @ 5V, 50pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TSSOP
74LVC2G02DP,125 FAQ
1.How can I place an order for 74LVC2G02DP,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC2G02DP,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC2G02DP,125 reliable?
The price and inventory of 74LVC2G02DP,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC2G02DP,125 is usually 5 days.
3.What payment methods are accepted for 74LVC2G02DP,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC2G02DP,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC2G02DP,125?
74LVC2G02DP,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC2G02DP,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC2G02DP,125?
For technical support, including 74LVC2G02DP,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC2G02DP,125 requirements.
6.How does Aetrix verify that 74LVC2G02DP,125 is sourced from the original manufacturer or authorized distributors?
All 74LVC2G02DP,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC2G02DP,125 meets industry standards.
7.What is the process for return or replacement of 74LVC2G02DP,125?
All 74LVC2G02DP,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC2G02DP,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC2G02DP,125 part is unused and in its original packaging.
Return procedure for 74LVC2G02DP,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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