Nexperia USA Inc. 74LVC2G06GV,125

Overview

74LVC2G06GV,125 from Nexperia is a dual CMOS inverter with open-drain outputs, designed for level translation between 3.3 V and 5 V logic domains. It features Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and operates across 1.65 V to 5.5 V supply. Used in I²C bus pull-up interfaces, GPIO expansion, and mixed-voltage sensor interfacing.

For engineers reviewing the 74LVC2G06GV,125 datasheet, 74LVC2G06GV,125 pinout, 74LVC2G06GV,125 application, or 74LVC2G06GV,125 equivalent, key selection criteria include open-drain drive capability (–24 mA at 3.0 V), input overvoltage tolerance to 5.5 V, IOFF-enabled backflow prevention during power sequencing, and –40 °C to +125 °C industrial temperature rating.

Technical Context

This device integrates two independent inverters, each with Schmitt-trigger inputs enabling robust operation with slow-rising signals and high noise immunity. The open-drain outputs require external pull-ups and support wired-AND logic, I²C-compatible bidirectional signaling, and voltage-level translation without direction control.

IOFF circuitry actively disables outputs when VCC = 0 V, blocking reverse current flow from powered downstream nodes-critical for hot-swap and partial-power-down systems. Input tolerance up to 5.5 V allows direct connection to 5 V sources even when VCC is 1.8 V or 3.3 V.

Key Specifications

Pinout & Package

74LVC2G06GV,125 uses the SOT457 (SC-74/TSOP6) package: plastic surface-mounted, 6-lead, body size 2.5 mm × 1.3 mm × 0.95 mm, with gull-wing leads and pin 1 indicator below marking code "V06".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual open-drain inverter applications.

Compared with 74LVC2G06GV,125, the GW variant offers easier assembly but larger area, while the SN74LVC2G06DBVR omits critical IOFF protection-making the GV the sole choice for robust hot-swap and multi-rail power sequencing designs.

Availability

74LVC2G06GV,125 is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and IoT sensor node designs requiring stable component supply across extended temperature ranges and mixed-voltage interfaces.

Supply support for 74LVC2G06GV,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, discrete, and MOSFET solutions for automotive, industrial, and consumer markets.

The 74LVC2G06 series belongs to Nexperia's LVC logic family, engineered for low-voltage operation, mixed-signal interfacing, and robustness in harsh environments-specifically targeting voltage translation and noise-immune digital control.

FAQ

Can 74LVC2G06GV,125 be used as a level shifter between 1.8 V and 5 V logic?

Yes. Its inputs tolerate up to 5.5 V regardless of VCC, and it operates down to 1.65 V. When VCC = 1.8 V, the 5 V input is safely clamped and translated to a 1.8 V-compatible open-drain output-enabling unidirectional 5 V → 1.8 V shifting with external pull-up to 1.8 V.

Does 74LVC2G06GV,125 support true bidirectional level shifting like dedicated I²C translators?

No. It is not inherently bidirectional. However, its dual open-drain outputs allow implementation of I²C-compatible bus translation when paired with appropriate pull-ups on both sides-leveraging the wired-AND nature of open-drain topology, not internal bidirectional circuitry.

What is the maximum capacitive load the 74LVC2G06GV,125 can drive reliably?

Test data specifies dynamic performance up to 50 pF load capacitance at VCC ≥ 2.7 V. With 24 mA sink capability at 3.0 V and typical propagation delay of 2.3 ns, it reliably drives standard I²C buses (≤400 pF total) when used with appropriate pull-up resistors per bus speed requirements.

Is the IOFF feature active only when VCC is exactly 0 V, or does it engage during brown-out conditions?

IOFF activates when VCC falls below approximately 0.2 V-verified by leakage testing at VCC = 0 V. During brown-out (e.g., VCC = 0.8 V), IOFF is inactive; outputs remain functional but may exhibit degraded noise immunity and increased static current. System design must ensure VCC fully disconnects to guarantee IOFF protection.