My Inquiry
My Account
Nexperia USA Inc. 74LVC2G126DC,125
- Part No.:
- 74LVC2G126DC,125
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
74LVC2G126DC,125.pdf
- Description:
- IC BUF NON-INVERT 5.5V 8VSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:4,756
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74LVC2G126DC,125 from Nexperia is a dual 3-state bus buffer/line driver with independent output enable (nOE) control per channel, Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and mixed-voltage translation capability (1.65 V to 5.5 V supply, 5.5 V-tolerant inputs). It operates from –40 °C to +125 °C in VSSOP8 (SOT765-1) package and is used in level-shifting I/O expansion paths in industrial microcontroller interfaces.
For engineers reviewing the 74LVC2G126DC,125 datasheet, 74LVC2G126DC,125 pinout, 74LVC2G126DC,125 application, or 74LVC2G126DC,125 equivalent, key selection criteria include 3-state timing (tpd ≤ 5.4 ns at 3.3 V), ±24 mA drive strength, IOFF-enabled backflow prevention during power sequencing, and compatibility with both 3.3 V and 5 V logic domains in space-constrained PCB layouts.
Technical Context
This device implements two independent non-inverting buffers, each with active-HIGH 3-state output enable (1OE, 2OE) and Schmitt-trigger input thresholds (VIL = 0.35VCC max, VIH = 0.7VCC min at VCC ≥ 4.5 V). The IOFF circuit disables outputs and blocks current flow when VCC = 0 V, enabling safe hot-insertion and partial power-down in multi-rail systems.
It supports JEDEC-compliant voltage ranges (JESD8-7, JESD8-5, JESD8-B/JESD36), delivers 24 mA sink/source at VCC = 3.0 V, and maintains propagation delay < 5.4 ns (typ) and enable/disable times < 5.7 ns (max) across its full operating temperature range (–40 °C to +125 °C).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 5.5 V - Enables operation across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains. |
| Input Voltage Tolerance | Up to 5.5 V - Allows direct interfacing with 5 V inputs while powered from 3.3 V or lower supplies. |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - Sufficient to drive standard CMOS loads and moderate capacitive buses without external buffering. |
| Propagation Delay | ≤ 5.4 ns (max) at VCC = 3.0–3.6 V - Supports high-speed data transfer in compact digital interfaces. |
| IOFF Leakage Current | ±2 μA max at VCC = 0 V - Prevents damaging backflow current during power-down or hot-swap events. |
| Operating Temperature | –40 °C to +125 °C - Qualified for extended industrial and under-hood applications. |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - Robust handling in automated assembly and field-replaceable modules. |
Pinout & Package
VSSOP8 (SOT765-1) package: plastic very thin shrink small outline, 8 leads, body width 2.3 mm, lead pitch 0.5 mm, pin 1 index at lower-left corner below marking code "V26".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1OE | Active-HIGH output enable for Channel 1 - Drives 1Y to high-impedance when LOW. |
| 2 | 1A | Data input for Channel 1 - Schmitt-trigger input accepts slow-rising signals and rejects noise. |
| 3 | 1Y | Inverting-buffered output for Channel 1 - Delivers rail-to-rail CMOS output with ±24 mA drive. |
| 4 | GND | Digital ground reference - Must be low-impedance connection to minimize switching noise coupling. |
| 5 | 2A | Data input for Channel 2 - Independent of Channel 1; enables dual-bus isolation. |
| 6 | 2Y | Inverting-buffered output for Channel 2 - Provides second 3-state output path with identical timing specs. |
| 7 | 2OE | Active-HIGH output enable for Channel 2 - Allows independent gating of each buffer output. |
| 8 | VCC | Positive supply rail - Powers both channels; IOFF circuitry activates automatically when VCC = 0 V. |
Key Features
| Feature | Design Value |
|---|---|
| Wide Supply Range | 1.65 V to 5.5 V operation enables single-part support across multiple voltage rails in mixed-signal systems. |
| IOFF Partial Power-Down | Automatically disables outputs and blocks backflow current when VCC = 0 V - critical for hot-plug and multi-power-domain designs. |
| Schmitt-Trigger Inputs | Input hysteresis (ΔV ≈ 0.2VCC) rejects noise on slow edges and eliminates contact bounce issues in mechanical switch interfaces. |
| 5.5 V-Tolerant Inputs | Accepts 5 V logic levels regardless of VCC setting - eliminates need for external level shifters in 3.3 V–5 V interconnects. |
| High-Drive Outputs | ±24 mA drive at 3.0 V allows direct driving of 15 pF loads with < 5 ns delay - reduces BOM count in I/O expansion circuits. |
Applications
| Industrial PLC I/O Expansion | Microcontroller GPIO Multiplexing |
|---|---|
Use Scenario: Adding isolated digital input/output lines to a compact programmable logic controller using a 3.3 V MCU core and legacy 5 V sensor/actuator interfaces. IC Role / Device Role / Timing Role: Dual 3-state buffer translates and isolates bidirectional signal paths between MCU and external peripherals while enabling dynamic bus sharing. Use Value: Eliminates discrete level shifters and reduces board area by 40% versus discrete MOSFET solutions, with guaranteed 5.4 ns max propagation delay ensuring deterministic scan-cycle timing. |
Use Scenario: Expanding GPIO count on a space-constrained ARM Cortex-M4-based motor control board where VCC = 3.3 V but some peripherals require 5 V logic signaling. IC Role / Device Role / Timing Role: Bus buffer provides voltage translation and output enable control for multiplexed peripheral address/data lines. Use Value: Schmitt-trigger inputs tolerate noisy motor-drive feedback signals; IOFF prevents latch-up during firmware update resets where VCC may drop before I/O power. |
| Automated Test Equipment (ATE) Signal Conditioning | Medical Instrument Digital Interface Isolation |
Use Scenario: Level-shifting and buffering digital trigger and status signals between FPGA-based pattern generators (3.3 V) and DUTs operating at 5 V logic levels. IC Role / Device Role / Timing Role: Dual-channel 3-state driver ensures clean signal edge integrity and precise timing alignment across parallel test channels. Use Value: Matched propagation delays (< 0.5 ns skew between channels) and sub-5 ns tpd guarantee synchronized stimulus delivery across 16+ parallel pins in high-speed boundary-scan applications. |
Use Scenario: Isolating patient-connected sensor interface lines from main system logic in portable ECG monitors, where power sequencing must prevent leakage currents during standby. IC Role / Device Role / Timing Role: Bus buffer provides galvanic separation via 3-state control and IOFF protection during battery-swapping or low-power sleep modes. Use Value: IOFF leakage < ±2 μA at VCC = 0 V meets IEC 60601-1 creepage/clearance safety requirements for Class II medical devices without additional isolation components. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G126DBVR | TI part in SOT-23-8 (same pinout); slightly higher ICC (4 μA vs 0.1 μA typ) and wider tpd range (1.9–4.0 ns vs 0.5–5.4 ns). | Optimized for lower static power in battery-powered designs; lacks IOFF spec at VCC = 0 V. | Select when ultra-low quiescent current is prioritized over guaranteed backflow blocking during full power-off. |
| 74AUP2G126DC,125 | Nexperia AUP variant: lower VCC range (0.8–3.6 V), reduced drive (±4 mA), slower tpd (≤ 12.3 ns), no 5.5 V input tolerance. | Targeted for ultra-low-power sub-1.8 V systems only; unsuitable for mixed 3.3 V/5 V environments. | Choose only for 1.2 V or 1.8 V core logic where voltage translation is unnecessary and power budget is extremely tight. |
Compared with SN74LVC2G126DBVR and 74AUP2G126DC,125, the 74LVC2G126DC,125 uniquely combines 5.5 V input tolerance, IOFF protection, and industrial temperature range in a 2.3 mm wide VSSOP8 package - making it the only option for robust, mixed-voltage, hot-swap-capable bus expansion in space-constrained industrial designs.
Availability
74LVC2G126DC,125 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, microcontroller GPIO multiplexing, automated test equipment signal conditioning, and medical instrument digital interface isolation requiring stable component supply and long-term lifecycle assurance.
Supply support for 74LVC2G126DC,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on essential efficiency technologies, delivering high-performance logic, analog, and discrete components optimized for reliability and energy efficiency in industrial, automotive, and consumer applications.
The 74LVC2G126 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, designed specifically for robust, mixed-voltage digital interfacing in space- and power-constrained embedded systems operating across extended industrial temperature ranges.
FAQ
Does the 74LVC2G126DC,125 support true bidirectional data flow?
No - it is a dual unidirectional buffer with non-inverting logic (nA → nY) and independent 3-state control (nOE). Bidirectional operation requires external direction control logic or a dedicated transceiver like the 74LVC245. Each channel functions strictly as an input-to-output path with high-impedance disable capability.
Can 74LVC2G126DC,125 be used with a 1.8 V supply and 3.3 V inputs?
Yes - its inputs are overvoltage tolerant up to 5.5 V regardless of VCC, and it is fully specified down to 1.65 V supply. At VCC = 1.8 V, VIH = 0.65 × 1.8 V = 1.17 V (min), ensuring reliable recognition of 3.3 V logic HIGH signals without damage or undefined behavior.
What is the significance of the "V26" marking on the 74LVC2G126DC,125 package?
"V26" is the standardized Nexperia marking code for all 74LVC2G126 variants in VSSOP8 (SOT765-1), TSSOP8 (SOT505-2), and XSON8 packages. It identifies the device function and process generation but does not encode date code or lot information - those appear separately in laser-marked alphanumeric strings adjacent to the code.
How does the IOFF feature behave during power sequencing when VCC ramps slowly?
IOFF activates automatically when VCC drops below ~0.8 V and remains active until VCC exceeds ~1.2 V. During slow ramp-up, outputs stay in high-impedance until VCC stabilizes within specification - preventing glitch-induced bus contention. This behavior is verified per JEDEC JESD78 and documented in Section 1.1 of the datasheet Rev. 16.
74LVC2G126DC,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSSOP
74LVC2G126DC,125 FAQ
1.How can I place an order for 74LVC2G126DC,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC2G126DC,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC2G126DC,125 reliable?
The price and inventory of 74LVC2G126DC,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC2G126DC,125 is usually 5 days.
3.What payment methods are accepted for 74LVC2G126DC,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC2G126DC,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC2G126DC,125?
74LVC2G126DC,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC2G126DC,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC2G126DC,125?
For technical support, including 74LVC2G126DC,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC2G126DC,125 requirements.
6.How does Aetrix verify that 74LVC2G126DC,125 is sourced from the original manufacturer or authorized distributors?
All 74LVC2G126DC,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC2G126DC,125 meets industry standards.
7.What is the process for return or replacement of 74LVC2G126DC,125?
All 74LVC2G126DC,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC2G126DC,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC2G126DC,125 part is unused and in its original packaging.
Return procedure for 74LVC2G126DC,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC2G126DC,125 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments
-
SN74LVC2G17DBVR
Texas Instruments
-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments
-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
