Texas Instruments 74LVC2G126DCTRG4
- Part No.:
- 74LVC2G126DCTRG4
- Manufacturer:
- Texas Instruments
- Package:
- 8-LSSOP, 8-MSOP (0.110", 2.80mm Width)
- Datasheet:
-
74LVC2G126DCTRG4.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V SM8
- Quantity:
- Payment:

- Shipping:

Inventory:1,141
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74LVC2G126DCTRG4 from Texas Instruments is a dual noninverting bus buffer gate with 3-state outputs, designed for 1.65 V to 5.5 V operation. It provides ±24 mA output drive at 3.3 V, achieves 4 ns max propagation delay at 3.3 V, and supports 5.5 V-tolerant inputs-enabling voltage translation from 5 V down to VCC level in mixed-voltage logic interfaces.
For engineers reviewing the 74LVC2G126DCTRG4 datasheet, 74LVC2G126DCTRG4 pinout, 74LVC2G126DCTRG4 application, or 74LVC2G126DCTRG4 equivalent, this device serves as a high-speed, low-power, 3-state buffer for bidirectional bus isolation, LED driving, and signal conditioning in industrial control, video infrastructure, and high-speed data acquisition systems.
Technical Context
The 74LVC2G126DCTRG4 implements two independent noninverting buffers, each with dedicated active-low output-enable (1OE, 2OE) control. Its Ioff feature disables outputs and blocks current backflow when VCC = 0 V, supporting live insertion and partial-power-down modes. The device operates across –40°C to +125°C and maintains rail-to-rail output swing (VOH ≥ VCC – 0.1 V, VOL ≤ 0.55 V at 24 mA).
It features 5.5 V-tolerant inputs regardless of VCC level, enabling seamless interfacing between 5 V legacy logic and lower-voltage domains (e.g., 3.3 V or 1.8 V). Input transition rate limits (5–20 ns/V) and low dynamic power (Cpd = 20 pF at 3.3 V) ensure clean signal integrity up to 100 MHz operation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - supports mixed-voltage system integration and down-translation (e.g., 5 V input → 3.3 V output) |
| Max Propagation Delay | 4 ns at VCC = 3.3 V - enables timing-critical paths in high-speed digital interfaces up to ~100 MHz |
| Output Drive | ±24 mA at VCC = 3.3 V - sufficient to drive multiple CMOS loads or LEDs without external amplification |
| Input Voltage Tolerance | Up to 5.5 V independent of VCC - eliminates need for level-shifter ICs when interfacing 5 V controllers to 3.3 V buses |
| Ioff Current | ±10 µA max at VI/VO = 5.5 V and VCC = 0 V - prevents damaging back-current during hot-swap or partial power-down |
| ESD Rating | 2000 V HBM, 1000 V CDM - meets industrial-grade robustness requirements for board-level reliability |
| Operating Temperature | –40°C to +125°C - qualified for under-hood automotive, industrial motor control, and telecom infrastructure |
Pinout & Package
74LVC2G126DCTRG4 uses the SM8 (SSOP-8) package, measuring 2.95 mm × 2.80 mm with 0.65 mm lead pitch. It is RoHS-compliant, lead-finished with NiPdAu, and rated MSL-1 (260°C peak reflow).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE | Active-low enable for Channel 1 | Drives 1Y high-impedance when low; ties to VCC via pulldown resistor for power-up safety |
| 1A | Noninverting input for Channel 1 | Accepts 0–5.5 V signals; compatible with 5 V TTL and 3.3 V LVC logic families |
| 1Y | Noninverting buffered output for Channel 1 | 3-state capable; sinks/sours ±24 mA at 3.3 V with rail-aligned VOH/VOL |
| 2A | Noninverting input for Channel 2 | Electrically isolated from Channel 1; identical voltage tolerance and timing behavior |
| 2OE | Active-low enable for Channel 2 | Independent control allows asymmetric bus gating (e.g., one channel always enabled) |
| 2Y | Noninverting buffered output for Channel 2 | Matches 1Y performance; supports wired-OR configurations when used with external pull-ups |
| GND | Ground reference | Single ground pin shared by both channels; requires low-inductance PCB connection |
| VCC | Power supply | Supplies both buffers; requires local 0.1 µF ceramic bypass capacitor per VCC pin |
Key Features
| Feature | Design Value |
|---|---|
| 5.5 V-tolerant inputs | Enables direct interface with 5 V microcontrollers or FPGAs without external level shifters |
| Ioff partial-power-down | Prevents back-drive current and latch-up when VCC is off-critical for hot-pluggable modules |
| NanoFree™ packaging | SM8 footprint minimizes PCB area vs. standard SOIC-8 while maintaining hand-solderability |
| Low ground bounce (VOLP < 0.8 V) | Reduces noise coupling into adjacent analog or RF circuits on shared PCB layers |
| Rail-to-rail output swing | Ensures full logic margin at both extremes (VOH ≥ VCC – 0.1 V, VOL ≤ 0.55 V @ 24 mA) |
Applications
| Cable Modem Termination Systems | High-Speed Data Acquisition |
|---|---|
|
Use Scenario: Isolating upstream/downstream data paths between DOCSIS PHY and MAC layers under varying voltage domains. IC Role / Device Role / Timing Role: Dual-channel 3-state buffer gates isolate bidirectional serial buses while enabling dynamic bandwidth allocation. Use Value: 5.5 V-tolerant inputs accept legacy 5 V PHY signals; ±24 mA drive ensures signal integrity over long traces to FPGA-based MAC processors. |
Use Scenario: Conditioning parallel ADC output lines before feeding into an FPGA or microcontroller with lower I/O voltage. IC Role / Device Role / Timing Role: Noninverting buffer with independent OE control synchronizes multi-channel sample capture and reduces fanout loading. Use Value: 4 ns max tpd preserves timing margins in 100 MSPS sampling systems; Ioff prevents data corruption during FPGA configuration reset. |
| Military Radar Signal Processing | Video Broadcasting Infrastructure |
|
Use Scenario: Interfacing radiation-hardened 5 V sensor front-ends to 3.3 V DSP subsystems in airborne radar platforms. IC Role / Device Role / Timing Role: Voltage-translating bus buffer isolates sensitive processing cores from noisy analog sensor domains. Use Value: –40°C to +125°C rating ensures operation in avionics bays; 2000 V HBM ESD withstand protects against field-induced transients. |
Use Scenario: Driving multiple SDI serializer inputs from a single video processor output in IP-based transcoding platforms. IC Role / Device Role / Timing Role: High-drive buffer distributes clock/data signals across redundant video paths with matched skew. Use Value: Low Cpd (20 pF) and fast edge rates minimize jitter accumulation; SM8 package supports dense layout in compact broadcast encoders. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G125DCTRG4 | Inverting output logic (Y = A̅), otherwise identical electrical specs and package | Required where signal polarity inversion is needed in bus arbitration or enable sequencing | Select when functional inversion is required; pinout and timing match 74LVC2G126DCTRG4 exactly |
| 74LVC2G126DCUTG4 | VSSOP-8 (DCU) package: 2.30 mm × 2.00 mm, same electrical specs, different thermal resistance (RθJA = 227°C/W) | Better suited for space-constrained layouts; slightly higher thermal impedance than SM8 | Choose for ultra-compact designs where PCB real estate is critical and thermal headroom permits |
Compared with SN74LVC2G125DCTRG4, 74LVC2G126DCTRG4 provides noninverting logic essential for transparent bus buffering; compared with 74LVC2G126DCUTG4, it offers lower thermal resistance (220°C/W vs. 227°C/W) and larger pad geometry for improved manufacturability in high-volume SMT lines.
Availability
74LVC2G126DCTRG4 is available at Aetrix Electronics and suitable for cable modem termination systems, high-speed data acquisition, and military radar signal processing requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LVC2G126DCTRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of expertise in high-reliability interface ICs.
The SN74LVC2G126 product line delivers dual 3-state buffers optimized for voltage translation, bus isolation, and signal integrity in industrial, communications, and defense systems operating from 1.65 V to 5.5 V.
FAQ
What is the maximum operating temperature range for the 74LVC2G126DCTRG4?
The 74LVC2G126DCTRG4 is specified for continuous operation from –40°C to +125°C ambient temperature. This wide range is validated per JEDEC JESD78 latch-up testing and supported by thermal metrics including RθJA = 220°C/W for the DCT package, making it suitable for under-hood automotive, industrial motor drives, and telecom infrastructure deployments where thermal stress is significant. All electrical parameters in the datasheet are guaranteed across this full range.
Does the 74LVC2G126DCTRG4 support 5 V input signals when powered at 3.3 V?
Yes, the 74LVC2G126DCTRG4 supports input voltages up to 5.5 V regardless of VCC level-including when VCC = 3.3 V. This 5 V tolerance is explicitly documented in the "Recommended Operating Conditions" table and enables direct interfacing with legacy 5 V microcontrollers, FPGAs, or logic families without external level shifters. The input clamp current rating (±50 mA) and Ioff protection further ensure safe operation during voltage domain transitions.
What is the purpose of the Ioff feature in the 74LVC2G126DCTRG4?
The Ioff feature in the 74LVC2G126DCTRG4 disables all outputs and blocks current flow through the device when VCC = 0 V, preventing damaging back-current from live signal lines into a powered-down subsystem. This capability supports live insertion, partial-power-down modes, and back-drive protection-critical for modular systems like pluggable video encoder cards or hot-swappable industrial I/O modules where subsystems may be powered independently.
Can the 74LVC2G126DCTRG4 drive LEDs directly?
Yes, the 74LVC2G126DCTRG4 can drive LEDs directly: each output delivers ±24 mA at 3.3 V, sufficient for standard indicator LEDs (e.g., 2–20 mA typical) without external current-limiting resistors if configured as a sink driver with anode tied to VCC. For higher-brightness or multi-LED loads, external resistors are recommended to maintain VOL ≤ 0.55 V and avoid exceeding the 50 mA per-output absolute maximum rating specified in Section 6.1.
Is the 74LVC2G126DCTRG4 pin-compatible with other members of the SN74LVC2Gxx family?
The 74LVC2G126DCTRG4 shares the same SM8 (DCT) 8-pin footprint and pinout with other SN74LVC2Gxx dual-gate variants such as SN74LVC2G125DCTRG4 (inverting) and SN74LVC2G00DCTRG4 (dual NAND), but logic function and enable polarity differ. While mechanical compatibility exists, functional substitution requires verification of truth tables, enable polarity (active-low OE), and output drive direction-especially for bus isolation or wired-OR applications where signal polarity and timing alignment are critical.
74LVC2G126DCTRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 8-LSSOP, 8-MSOP (0.110", 2.80mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SM8
74LVC2G126DCTRG4 FAQ
1.How can I place an order for 74LVC2G126DCTRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC2G126DCTRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC2G126DCTRG4 reliable?
The price and inventory of 74LVC2G126DCTRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC2G126DCTRG4 is usually 5 days.
3.What payment methods are accepted for 74LVC2G126DCTRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC2G126DCTRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC2G126DCTRG4?
74LVC2G126DCTRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC2G126DCTRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC2G126DCTRG4?
For technical support, including 74LVC2G126DCTRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC2G126DCTRG4 requirements.
6.How does Aetrix verify that 74LVC2G126DCTRG4 is sourced from the original manufacturer or authorized distributors?
All 74LVC2G126DCTRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC2G126DCTRG4 meets industry standards.
7.What is the process for return or replacement of 74LVC2G126DCTRG4?
All 74LVC2G126DCTRG4 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC2G126DCTRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC2G126DCTRG4 part is unused and in its original packaging.
Return procedure for 74LVC2G126DCTRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC2G126DCTRG4 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

