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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

NXP Semiconductors 74LVC2G126GD,125

Name: 74LVC2G126GD,125
Brand: NXP Semiconductors
SKU: 74LVC2G126GD,125
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 74LVC2G126GD,125

Manufacturer:: NXP Semiconductors

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: -

Datasheet:: 74LVC2G126GD,125.pdf

Description:: IC BUS BUFF DVR TRI-ST DL 8XSON

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Product details

Overview

74LVC2G126GD,125 from Nexperia is a dual 3-state bus buffer/line driver with independent output enable inputs (1OE, 2OE), Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and 1.65 V to 5.5 V supply operation. It supports mixed-voltage translation between 3.3 V and 5 V systems and delivers ±24 mA output drive at VCC = 3.0 V. Used in industrial I/O expansion and FPGA/CPU peripheral interfacing.

For engineers reviewing the 74LVC2G126GD,125 datasheet, 74LVC2G126GD,125 pinout, 74LVC2G126GD,125 application, or 74LVC2G126GD,125 equivalent, key selection criteria include 3-state timing (tpd ≤ 4.0 ns @ 5.5 V), IOFF-enabled backflow prevention during power sequencing, Schmitt-trigger input hysteresis (≥ 0.3 V typical), and XSON8 package thermal performance (Ptot derating starts at 68 °C).

Technical Context

This device implements two independent non-inverting buffers, each with active-HIGH 3-state control via dedicated OE inputs. The Schmitt-trigger inputs provide ≥ 0.3 V hysteresis across all VCC ranges, enabling robust operation with slow-rising signals from microcontrollers or sensors.

IOFF circuitry actively disables outputs when VCC = 0 V, blocking reverse current flow up to ±50 mA, making it suitable for hot-swap and partial-power-down architectures. Input overvoltage tolerance to 5.5 V allows safe interfacing with 5 V logic while operating from 1.65 V supplies.

Key Specifications

Parameter	Value and Actual Design Meaning
Supply voltage range	1.65 V to 5.5 V - Enables single-supply operation across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains.
Output drive strength	±24 mA @ VCC = 3.0 V - Sufficient to drive 50 Ω transmission lines or multiple CMOS loads without external buffering.
Propagation delay	≤ 4.0 ns @ VCC = 5.5 V - Supports high-speed data routing in sub-10 ns timing-critical paths.
IOFF leakage	±2 μA @ VCC = 0 V - Prevents damaging backfeed current during system power sequencing or standby modes.
Input hysteresis	≥ 0.3 V typical - Tolerates slow edges (Δt/ΔV down to 10 ns/V) from mechanical switches or long traces.
ESD rating	HBM > 2000 V, CDM > 1000 V - Meets industrial-grade ESD robustness per JS-001/JS-002 Class 2/C3.
Operating temperature	–40 °C to +125 °C - Qualified for extended industrial and under-hood applications.

Pinout & Package

XSON8 package (SOT1089): plastic extremely thin small outline, no leads, 8 terminals, body size 1.35 × 1.0 × 0.5 mm, pin 1 index in lower-left corner below marking code "VN".

Pin/Terminal	Circuit Role	Design Meaning
1	1OE	Active-HIGH output enable for first buffer - drives 1Y to high-impedance when LOW.
2	VCC	Main supply rail - powers both buffers and internal logic; decoupling required within 1 mm.
3	1A	Data input for first buffer - Schmitt-triggered, tolerant of slow edges and noise.
4	2OE	Active-HIGH output enable for second buffer - independent control enables asymmetric bus gating.
5	2Y	Data output for second buffer - 3-state, ±24 mA capable, IOFF-protected.
6	1Y	Data output for first buffer - electrically isolated from 2Y; supports bidirectional bus arbitration.
7	GND	Ground reference - must be low-inductance connection; shared with VCC return path.
8	2A	Data input for second buffer - identical electrical behavior to 1A; enables dual-channel signal conditioning.

Key Features

Feature	Design Value
Wide supply range	1.65 V to 5.5 V - Eliminates level shifters in mixed-voltage systems (e.g., 3.3 V MCU to 5 V sensor interface).
Schmitt-trigger inputs	≥ 0.3 V hysteresis - Rejects noise on long PCB traces or switch bounce without external RC filtering.
IOFF partial power-down	Blocks backflow current at VCC = 0 V - Enables safe insertion/removal in live backplanes or modular systems.
Overvoltage-tolerant inputs	Rated to 5.5 V regardless of VCC - Allows direct connection to 5 V sources even when powered from 1.8 V.
High noise immunity	CMOS input structure with > 40 % VCC noise margin - Resists EMI in motor-drive or switching-power environments.

Applications

Industrial PLC I/O Expansion

FPGA Peripheral Interface

Use Scenario: Isolating and buffering digital I/O signals between a PLC main controller and field-mounted sensors/actuators operating at different voltage levels.

IC Role / Device Role / Timing Role: Dual 3-state buffer providing direction-controlled signal routing and voltage translation between 24 V logic (via level-shifter front-end) and 3.3 V FPGA I/O banks.

Use Value: IOFF prevents backfeed during module hot-swap; Schmitt inputs reject EMI from nearby contactors and solenoids.

Use Scenario: Interfacing FPGA GPIO banks to legacy parallel peripherals (e.g., LCD controllers, SRAM, ADCs) requiring precise 3-state control and fast edge rates.

IC Role / Device Role / Timing Role: Bus driver managing bidirectional data flow on shared address/data buses, with independent OE control per channel for arbitration.

Use Value: 4.0 ns max propagation delay ensures setup/hold compliance at 100 MHz bus speeds; ±24 mA drive sustains signal integrity over 10 cm traces.

Automotive Body Control Module

Medical Instrument Data Acquisition

Use Scenario: Signal conditioning between microcontroller GPIOs and external CAN transceiver control lines or LED driver enable inputs in body electronics.

IC Role / Device Role / Timing Role: Level-translating buffer isolating 5 V automotive subsystems from 3.3 V MCU logic, with fail-safe IOFF during battery brownout.

Use Value: –40 °C to +125 °C qualification matches under-hood thermal requirements; 5.5 V input tolerance handles load-dump transients.

Use Scenario: Routing analog-to-digital conversion trigger signals and status flags between precision ADCs and ARM Cortex-M microcontrollers in portable diagnostic equipment.

IC Role / Device Role / Timing Role: Low-noise, high-immunity buffer ensuring clean timing edges for synchronous sampling, immune to ECG/EEG amplifier interference.

Use Value: Schmitt-trigger inputs suppress coupling from adjacent high-gain analog stages; <100 μA ICC supports battery-powered operation.

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 3-state buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LVC2G126DBVR	TSSOP8 package (SOT23-8); higher thermal resistance (θJA = 210 K/W vs. 190 K/W for SOT1089); same electrical specs.	Better manual solderability but larger footprint; less suitable for ultra-compact portable designs.	Select for prototyping or low-volume assembly where rework access matters more than board area.
74LVC2G125GD,125	Inverting version (1A→1Y inverted); identical pinout, package, and timing; same IOFF/Schmitt features.	Required only where logic inversion is needed in signal path (e.g., active-low enable translation).	Choose only if system-level logic requires inversion; otherwise, 74LVC2G126GD,125 provides direct signal pass-through.

Compared with SN74LVC2G126DBVR, the 74LVC2G126GD,125 offers 15 % lower thermal resistance in XSON8, enabling higher sustained drive current in space-constrained layouts; versus 74LVC2G125GD,125, it eliminates need for external inverters in non-inverting bus applications, reducing BOM count and propagation delay.

Availability

74LVC2G126GD,125 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, FPGA peripheral interface, automotive body control modules, and medical instrument data acquisition requiring stable component supply across extended temperature ranges and mixed-voltage environments.

Supply support for 74LVC2G126GD,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer applications.

The 74LVC2G126 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, designed specifically for robust, low-power, mixed-voltage interfacing in space- and power-constrained embedded systems.

FAQ

What is the maximum allowable input voltage when VCC = 1.65 V?

The 74LVC2G126GD,125 supports overvoltage-tolerant inputs up to 5.5 V regardless of VCC level. When VCC = 1.65 V, inputs may safely swing from 0 V to 5.5 V without damage or latch-up, enabling direct connection to 5 V sources in level-translation applications.

Does the IOFF feature work when VCC is disconnected but GND remains connected?

Yes. IOFF activates when VCC = 0 V (disconnected or shorted), disabling both outputs and limiting OFF-state leakage to ±2 μA even with inputs or outputs biased to 5.5 V. This prevents backflow current through the device during hot-swap or partial system power-down scenarios.

Can this device drive a 50 Ω transmission line directly?

Yes. With ±24 mA output drive at VCC = 3.0 V and VOL ≤ 0.80 V at 24 mA, the device can terminate a 50 Ω line to ground or pull up to VCC with <1 V drop, supporting point-to-point signaling at up to 100 Mbps without external series termination.

Is the XSON8 package (SOT1089) compatible with standard reflow profiles?

Yes. The SOT1089 package is qualified for IPC/JEDEC J-STD-020D moisture sensitivity level 1 and supports peak reflow temperatures up to 260 °C. Its 0.5 mm profile and copper-leadframe construction ensure reliable solder joint formation using standard lead-free reflow profiles.

74LVC2G126GD,125 Specifications

Product attributes: Attribute value

Manufacturer:: NXP Semiconductors

Series:: 74LVC

Package/Case:: -

Packaging:: Bulk

Product Status:: Active

Logic Type:: -

Number of Elements:: -

Number of Bits per Element:: -

Input Type:: -

Output Type:: -

Current - Output High, Low:: -

Voltage - Supply:: -

Operating Temperature:: -

Grade:: -

Qualification:: -

Mounting Type:: -

Supplier Device Package:: -

74LVC2G126GD,125 FAQ

1.How can I place an order for 74LVC2G126GD,125 through Aetrix?

Please submit a Request for Quotation (RFQ) for 74LVC2G126GD,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 74LVC2G126GD,125 reliable?

The price and inventory of 74LVC2G126GD,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC2G126GD,125 is usually 5 days.

3.What payment methods are accepted for 74LVC2G126GD,125?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC2G126GD,125 transactions.

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4.How is shipping managed for 74LVC2G126GD,125?

74LVC2G126GD,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 74LVC2G126GD,125 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 74LVC2G126GD,125?

For technical support, including 74LVC2G126GD,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC2G126GD,125 requirements.

6.How does Aetrix verify that 74LVC2G126GD,125 is sourced from the original manufacturer or authorized distributors?

All 74LVC2G126GD,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC2G126GD,125 meets industry standards.

7.What is the process for return or replacement of 74LVC2G126GD,125?

All 74LVC2G126GD,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC2G126GD,125, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 74LVC2G126GD,125 part is unused and in its original packaging.

Return procedure for 74LVC2G126GD,125:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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