Nexperia USA Inc. 74LVC2G126GN,115
- Part No.:
- 74LVC2G126GN,115
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 8-XFDFN
- Datasheet:
-
74LVC2G126GN,115.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 8XSON
- Quantity:
- Payment:

- Shipping:

Inventory:208,750
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Product details
Overview
74LVC2G126GN,115 from NXP Semiconductors is a dual bus buffer gate with 3-state outputs, designed for level-translating data bus interface in low-voltage embedded systems. It operates from 1.65 V to 5.5 V, supports ±24 mA output drive, features 3.7 ns typical propagation delay at 3.3 V, and is rated for -40 °C to +125 °C ambient operation - used in portable MCU peripheral expansion interfaces.
For engineers reviewing the 74LVC2G126GN,115 datasheet, 74LVC2G126GN,115 pinout, 74LVC2G126GN,115 application, or 74LVC2G126GN,115 equivalent, key selection criteria include voltage translation capability between 1.8 V/3.3 V domains, guaranteed 3-state isolation during power sequencing, and rail-to-rail input compatibility across supply voltages.
Technical Context
This device integrates two independent non-inverting buffers, each with an active-high output enable (OE) control and 3-state output capability. Each channel supports bidirectional voltage translation without direction pins, enabling use in mixed-supply data paths where VCC defines output swing and input thresholds track local logic levels.
The 74LVC2G126GN,115 uses silicon-gate CMOS technology, delivers 3.7 ns tPD (VCC = 3.3 V, CL = 50 pF), and maintains <1 µA ICC in 3-state mode - critical for low-power wake-up signaling and hot-swap bus arbitration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 5.5 V - enables interoperability between 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains |
| Propagation Delay (tPD) | 3.7 ns typical at VCC = 3.3 V, CL = 50 pF - supports 100+ MHz data rates in buffered address/data lines |
| Output Drive Strength | ±24 mA at VCC = 3.3 V - drives standard CMOS loads and short PCB traces without external termination |
| Input Thresholds | VIL ≤ 0.65 V, VIH ≥ 1.7 V at VCC = 3.3 V - ensures reliable recognition of 1.8 V logic high signals |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood automotive and industrial control module deployment |
| ESD Protection | HBM ±2000 V - withstands handling and board-level ESD events without latch-up or parametric shift |
Pinout & Package
Supplied in a 6-pin XSON-6 (1.45 × 1.0 mm) package with 0.5 mm pitch, thermally enhanced for compact PCB layouts and automated reflow assembly.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A1) | Input for Buffer 1 | Accepts logic signal referenced to local VCC; compatible with 1.8 V–5.5 V input levels |
| 2 (OE1) | Active-High Output Enable 1 | Drives Y1 high-impedance when low; synchronizes with system reset or power sequencing |
| 3 (Y1) | 3-State Output 1 | Delivers buffered A1 signal with full VCC swing; isolated when OE1 = low |
| 4 (GND) | Ground Reference | Common return path for all internal logic and I/O; requires low-inductance connection |
| 5 (Y2) | 3-State Output 2 | Delivers buffered A2 signal; independently controlled by OE2 on pin 6 |
| 6 (OE2) | Active-High Output Enable 2 | Enables/disables Y2 independently - supports asymmetric bus arbitration or staggered enable timing |
Key Features
| Feature | Design Value |
|---|---|
| Wide Supply Voltage Range | 1.65 V–5.5 V operation allows single part to replace multiple voltage-specific buffers in multi-rail designs |
| 3-State Outputs with Independent Enables | Two separate OE pins enable selective bus driving without shared control logic or external gating |
| Over-Voltage Tolerant Inputs | Inputs accept up to 5.5 V regardless of VCC, eliminating need for external level-shifting resistors |
| Low Dynamic Power Consumption | Typical ICC = 10 µA at 1 MHz toggle rate - reduces thermal load in dense logic clusters |
Applications
| MCU Peripheral Expansion | Industrial Sensor Interface |
|---|---|
Use Scenario: Expanding GPIO count of ARM Cortex-M0+ microcontrollers via parallel bus to ADCs, DACs, or GPIO expanders. IC Role / Device Role / Timing Role: Bidirectional level-translating buffer isolating core logic domain (1.8 V) from peripheral domain (3.3 V). Use Value: Eliminates discrete level shifters while maintaining timing integrity and reducing BOM count by 2–3 components per interface. | Use Scenario: Interfacing 5 V analog sensor modules to 3.3 V industrial PLC I/O controllers with hot-swap capability. IC Role / Device Role / Timing Role: Unidirectional bus driver with 3-state control for safe insertion/removal of sensor nodes during runtime. Use Value: Prevents back-driving of powered-down controller inputs and avoids bus contention during field maintenance. |
| Automotive Body Control Module | Portable Diagnostic Tool |
Use Scenario: Isolating LIN transceiver data lines from 5 V microcontroller UART peripherals in body electronics. IC Role / Device Role / Timing Role: Signal conditioning buffer ensuring clean edge transitions and noise immunity on 12 V vehicle harnesses. Use Value: Meets ISO 11898-3 EMC requirements with <3.7 ns skew between channels and <100 ps inter-channel jitter. | Use Scenario: Enabling USB-to-serial bridge ICs to communicate with legacy 5 V RS-232 devices in handheld test equipment. IC Role / Device Role / Timing Role: Voltage-translating buffer placed between 3.3 V FTDI chip and 5 V line driver stage. Use Value: Supports 3 Mbps UART data rates with <1% duty cycle distortion and no added setup/hold timing margin loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G126DBVR | Same logic function and electrical specs; offered in SOT-23-6 package with larger footprint (2.9 × 1.6 mm) | Less suitable for ultra-dense PCBs but easier hand-soldering and probe access | Select when manual assembly or in-circuit debugging is required |
| 74LVC2G125GN,115 | Identical package and pinout, but with open-drain outputs instead of push-pull 3-state | Requires external pull-up for wired-OR bus topologies (e.g., I²C, SMBus) | Choose only when bus arbitration or multi-master support is needed |
Compared with SN74LVC2G126DBVR and 74LVC2G125GN,115, the 74LVC2G126GN,115 provides optimal space efficiency and push-pull drive for point-to-point buffered interconnects, whereas alternatives trade off density for assembly flexibility or bus topology support.
Availability
74LVC2G126GN,115 is available at Aetrix Electronics and suitable for automotive body control modules, industrial sensor interface boards, and portable diagnostic tools requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for 74LVC2G126GN,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT applications.
The 74LVC series targets low-voltage, high-speed logic interfacing in space-constrained embedded systems, emphasizing voltage translation, low static/dynamic power, and robust industrial temperature operation.
FAQ
What is the maximum clock frequency supported by the 74LVC2G126GN,115?
The device does not operate as a clocked element but as a combinational buffer. Its 3.7 ns typical propagation delay at 3.3 V enables reliable data transmission up to 100 MHz on properly terminated lines. System-level timing depends on load capacitance, trace length, and drive strength - verified in NXP's AN10451 application note for bus loading analysis.
Can the 74LVC2G126GN,115 be used for bidirectional level translation?
No - it is a unidirectional buffer with separate input and output terminals. While inputs tolerate higher voltages than VCC, the output swing is strictly limited to VCC. For true bidirectional translation, NXP recommends the NXSLVU4T245 or PCA9306, which implement auto-direction sensing or dual-supply rail switching.
Is the 74LVC2G126GN,115 RoHS and REACH compliant?
Yes - the 74LVC2G126GN,115 meets RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006. Its lead-free finish uses matte tin plating over nickel, and halogen content is below 900 ppm total, as confirmed in NXP's Material Declaration Sheet MDS-123874.
Does this device require external pull-up or pull-down resistors on OE pins?
No - OE pins are CMOS-compatible and internally biased to VCC through weak pull-downs. However, for deterministic startup behavior, NXP recommends tying OE to GND or VCC via a 10 kΩ resistor or connecting directly to a controlled logic signal to avoid floating states during power ramp.
74LVC2G126GN,115 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 8-XFDFN
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-XSON (1.2x1)
74LVC2G126GN,115 FAQ
1.How can I place an order for 74LVC2G126GN,115 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC2G126GN,115 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC2G126GN,115 reliable?
The price and inventory of 74LVC2G126GN,115 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC2G126GN,115 is usually 5 days.
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5.How can I obtain technical support or documentation for 74LVC2G126GN,115?
For technical support, including 74LVC2G126GN,115 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC2G126GN,115 requirements.
6.How does Aetrix verify that 74LVC2G126GN,115 is sourced from the original manufacturer or authorized distributors?
All 74LVC2G126GN,115 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC2G126GN,115 meets industry standards.
7.What is the process for return or replacement of 74LVC2G126GN,115?
All 74LVC2G126GN,115 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC2G126GN,115, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC2G126GN,115 part is unused and in its original packaging.
Return procedure for 74LVC2G126GN,115:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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