Nexperia USA Inc. 74LVC2G32GD,125

Overview

74LVC2G32GD,125 from Nexperia is a dual 2-input OR gate logic IC designed for level translation between 3.3 V and 5 V systems, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and operation across 1.65 V to 5.5 V supply. It delivers ±24 mA output drive at 3.0 V and supports industrial temperature range (–40 °C to +125 °C) in an XSON8 package (SOT1116, 1.2 × 1.0 × 0.35 mm).

For engineers reviewing the 74LVC2G32GD,125 datasheet, 74LVC2G32GD,125 pinout, 74LVC2G32GD,125 application, or 74LVC2G32GD,125 equivalent, this device serves as a compact, low-power logic building block for voltage-level interfacing, bus arbitration, and signal conditioning in space-constrained embedded control and I/O expansion circuits.

Technical Context

The 74LVC2G32GD,125 implements two independent OR gates with Schmitt-trigger inputs, enabling robust operation with slow-rising or noisy input signals. Its IOFF circuit actively disables outputs during power-down, preventing backflow current when VCC = 0 V - critical for hot-swap and mixed-voltage system integrity.

It complies with JEDEC standards JESD8-7 (1.65–1.95 V), JESD8-5 (2.3–2.7 V), JESD8C (2.7–3.6 V), and JESD36 (4.5–5.5 V), and supports overvoltage-tolerant inputs up to 5.5 V regardless of VCC, allowing direct connection to 5 V TTL sources while powered from 1.8 V or 3.3 V rails.

Key Specifications

Pinout & Package

XSON8 package (SOT1116): plastic extremely thin small outline, no leads, 8-terminal surface-mount, body dimensions 1.2 mm × 1.0 mm × 0.35 mm, thermal pad optional, pin 1 index located on lower-left corner below marking "VG".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual 2-input OR gate applications.

Compared with SN74LVC2G32DBVR, the 74LVC2G32GD,125 offers superior board-area efficiency and thermal performance in high-density layouts; compared with 74AUP2G32GS,132, it retains essential 5 V input compatibility at modest ICC trade-off - making it the preferred choice for robust, mixed-voltage logic interfacing.

Availability

74LVC2G32GD,125 is available at Aetrix Electronics and suitable for industrial sensor interfaces, USB-C power delivery control, automotive body electronics, and IoT edge node wake-up logic requiring stable component supply, long-term lifecycle assurance, and consistent XSON8 packaging.

Supply support for 74LVC2G32GD,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert specializing in high-performance, energy-efficient logic, analog, and discrete components, headquartered in Nijmegen, Netherlands.

The 74LVC2G32GD,125 belongs to Nexperia's LVC (Low-Voltage CMOS) logic family, engineered for voltage translation, noise-immune signal routing, and power-aware operation in space- and power-constrained embedded systems.

FAQ

What is the maximum input voltage the 74LVC2G32GD,125 can tolerate when VCC = 1.8 V?

The device accepts inputs up to 5.5 V regardless of VCC level - confirmed by "Overvoltage tolerant inputs to 5.5 V" in Section 2 and Table 5 (VI input voltage limit: –0.5 V to +6.5 V). This enables direct connection to 5 V TTL outputs while powered from 1.8 V, eliminating external level shifters in mixed-voltage designs.

Does the 74LVC2G32GD,125 support hot-swap or partial power-down operation?

Yes - its IOFF circuitry actively disables outputs and limits leakage to ±2 μA when VCC = 0 V, preventing damaging backflow current through powered-down sections of a system. This is explicitly specified in Section 1 ("fully specified for partial power down applications using IOFF") and Table 7 (IOFF power-off leakage current).

What is the propagation delay variation across temperature and voltage for the 74LVC2G32GD,125?

At VCC = 4.5–5.5 V, tpd ranges from 0.7 ns (min) to 4.0 ns (max) over –40 °C to +125 °C (Table 8). At VCC = 3.0–3.6 V, delay is 0.9–5.3 ns across the same range. These values include worst-case process, voltage, and temperature corners - no derating required for design-in.

Is the XSON8 package (SOT1116) of the 74LVC2G32GD,125 compatible with standard reflow profiles?

Yes - the SOT1116 package is qualified for IPC/JEDEC J-STD-020 moisture sensitivity level 1 (MSL1), supporting peak reflow temperatures up to 260 °C. Its 0.35 mm profile and copper-leadframe construction ensure reliable solder joint formation under standard lead-free reflow profiles without tombstoning or voiding concerns.