Nexperia USA Inc. 74LVC2G86DC,125
- Part No.:
- 74LVC2G86DC,125
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Gates and Inverters
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
74LVC2G86DC,125.pdf
- Description:
- IC GATE XOR 2CH 2-INP 8VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LVC2G86DC,125 from Nexperia is a dual 2-input EXCLUSIVE-OR gate in VSSOP8 package (SOT765-1), operating from 1.65 V to 5.5 V supply, featuring Schmitt-trigger inputs for noise immunity and IOFF circuitry enabling partial power-down mode. It supports mixed-voltage translation between 3.3 V and 5 V logic domains and is rated for -40 °C to +125 °C operation.
For engineers reviewing the 74LVC2G86DC,125 datasheet, 74LVC2G86DC,125 pinout, 74LVC2G86DC,125 application, or 74LVC2G86DC,125 equivalent, this device serves as a low-power, voltage-tolerant logic gate for level-shifting, parity generation, and digital signal conditioning in space-constrained industrial and embedded control systems.
Technical Context
This CMOS logic IC implements two independent XOR functions with rail-to-rail input tolerance up to 5.5 V and guaranteed switching down to 1.65 V VCC. Its Schmitt-trigger inputs provide hysteresis (typ. 0.3 V at VCC = 3.3 V), enabling robust operation with slow-rising signals in noisy environments.
The IOFF feature disables outputs when VCC = 0 V, preventing backflow current during hot-insertion or partial system power-down-critical for I²C bus isolation, FPGA configuration sequencing, and modular power management architectures.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65 V to 5.5 V - Enables direct interface with both 1.8 V, 2.5 V, 3.3 V, and 5 V logic families without external level shifters. |
| Input Voltage Tolerance | Up to 5.5 V - Allows 5 V inputs to be safely applied while powered from 1.65–3.3 V supplies, supporting mixed-voltage translation. |
| Propagation Delay | 0.8 ns (min) to 5.9 ns (max) at VCC = 3.0–3.6 V - Ensures deterministic timing in high-speed control loops and synchronous data paths. |
| Output Drive Strength | ±24 mA at VCC = 3.0 V - Sufficient to drive multiple LVC loads or moderate capacitive traces without buffering. |
| IOFF Leakage Current | ±2 μA max at VCC = 0 V - Limits backfeed current during partial power-down, protecting unpowered downstream circuitry. |
| Operating Temperature | -40 °C to +125 °C - Qualified for under-hood automotive modules, industrial PLCs, and extended-temperature sensor interfaces. |
| ESD Protection | HBM >2000 V, CDM >1000 V - Reduces susceptibility to handling damage and board-level ESD events in manufacturing and field service. |
Pinout & Package
VSSOP8 plastic very thin shrink small outline package (SOT765-1); 8 leads; body width 2.3 mm; lead length 0.5 mm; pin 1 index located on lower-left corner below marking code "V86".
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | 1A | First input of XOR gate 1 - Accepts Schmitt-triggered logic signal; tolerant to 5.5 V regardless of VCC. |
| 2 | VCC | Positive supply rail - Must be decoupled locally; powers both gates and internal IOFF control circuitry. |
| 3 | 1B | Second input of XOR gate 1 - Fully symmetrical with 1A; enables standard or inverted XOR function based on input pairing. |
| 4 | 1Y | Output of XOR gate 1 - Active-high, push-pull CMOS output; sinks or sources up to ±24 mA at VCC = 3.0 V. |
| 5 | 2Y | Output of XOR gate 2 - Electrically isolated from 1Y; supports independent routing for dual-channel logic functions. |
| 6 | 2B | Second input of XOR gate 2 - Matches 1B in electrical characteristics and timing behavior. |
| 7 | GND | Digital ground reference - Shared return path for both gates; must be low-impedance to minimize ground bounce. |
| 8 | 2A | First input of XOR gate 2 - Identical to 1A; allows concurrent evaluation of two independent XOR expressions. |
Key Features
| Feature | Design Value |
|---|---|
| Schmitt-trigger inputs | Provides 0.3–0.5 V hysteresis across VCC range, eliminating false triggering from slow or noisy edges in motor control feedback or sensor interfaces. |
| IOFF partial power-down | Disables outputs when VCC = 0 V, blocking back-current flow - essential for hot-swap I/O expansion cards and battery-backed subsystems. |
| Overvoltage-tolerant inputs | Accepts 5.5 V inputs while VCC is as low as 1.65 V, enabling seamless 5 V → 3.3 V level translation without external components. |
| Wide temperature range | Specified from -40 °C to +125 °C - Validated for use in engine control units, industrial inverters, and outdoor telecom equipment. |
| Low dynamic power | CPD = 15.8 pF per gate - Minimizes switching power in always-on status monitoring circuits and low-duty-cycle wake-up logic. |
Applications
| Industrial Sensor Interface | Motor Control Feedback |
|---|---|
|
Use Scenario: Detecting quadrature encoder phase mismatch in servo drives to identify mechanical slippage or misalignment. IC Role / Device Role / Timing Role: XOR gate compares A/B channel transitions to generate direction-agnostic error pulses synchronized to edge timing. Use Value: Schmitt-trigger inputs reject EMI-induced jitter on long encoder cables; IOFF prevents fault propagation during controller reset. |
Use Scenario: Generating enable/disable strobes for H-bridge gate drivers based on complementary PWM signals. IC Role / Device Role / Timing Role: Dual XOR evaluates rising/falling edge alignment between high-side and low-side control signals to prevent shoot-through. Use Value: Sub-6 ns propagation delay ensures precise dead-time validation; ±24 mA drive directly interfaces with gate driver inputs. |
| FPGA Configuration Bus | Secure Boot Integrity Check |
|
Use Scenario: Validating integrity of FPGA bitstream load by comparing checksum bits against expected parity values. IC Role / Device Role / Timing Role: XOR computes bitwise parity over configuration data lanes; outputs fed to status latch or interrupt generator. Use Value: 1.65–5.5 V operation matches FPGA I/O bank voltages; VSSOP8 footprint saves PCB area near BGA packages. |
Use Scenario: Performing real-time XOR-based checksum verification of boot firmware blocks before execution. IC Role / Device Role / Timing Role: Hardware-accelerated parity generator for tamper-evident memory readout in secure microcontrollers. Use Value: Low ICC (≤4 μA) enables always-on monitoring without impacting battery life; -40 °C to +125 °C rating suits automotive ECUs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 2-input XOR gate applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC2G86DCKR | Same logic function and IOFF support, but in SC70-6 (SOT363) package with only 6 pins - lacks dedicated GND and VCC pins for each gate; shares supply rails. | Lower pin count limits routing flexibility in dense layouts; thermal performance derates faster above 85 °C due to smaller package. | Select when board space is critical and thermal load is light; verify shared VCC/GND noise coupling in mixed-signal designs. |
| 74AUP2G86DC,125 | Ultra-low-power variant (ICC ≤ 0.5 μA) with slower max speed (tpd ≤ 11.3 ns at VCC = 3.3 V); identical VSSOP8 pinout and IOFF behavior. | Better suited for battery-powered IoT nodes requiring nanowatt standby, but unsuitable for >10 MHz clock-domain crossing or real-time control. | Choose for energy-constrained edge sensors; avoid in motor control or high-speed serial link monitoring where timing margin is tight. |
Compared with SN74LVC2G86DCKR and 74AUP2G86DC,125, the 74LVC2G86DC,125 delivers optimal balance of speed (≤5.9 ns), drive strength (±24 mA), and thermal robustness in VSSOP8 - making it preferred for industrial motion control and FPGA-adjacent logic where reliability and timing predictability are non-negotiable.
Availability
74LVC2G86DC,125 is available at Aetrix Electronics and suitable for industrial automation, motor control, and FPGA configuration requiring stable component supply across extended temperature ranges and multi-voltage system integration.
Supply support for 74LVC2G86DC,125 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer applications.
The 74LVC2G86 belongs to Nexperia's LVC logic family, engineered for low-voltage operation with robust noise immunity and mixed-voltage interoperability - targeting space-constrained, thermally demanding embedded control systems.
FAQ
Can 74LVC2G86DC,125 operate with 1.8 V supply while accepting 3.3 V inputs?
Yes. The device is specified for VCC = 1.65 V to 5.5 V and features overvoltage-tolerant inputs rated to 5.5 V regardless of supply voltage. At VCC = 1.8 V, inputs up to 3.3 V are safely accepted and correctly interpreted, enabling direct 3.3 V → 1.8 V level translation without external circuitry.
Does the IOFF feature require external control signals?
No. IOFF is fully automatic and requires no external enable/disable pin. When VCC drops to 0 V (e.g., during hot-swap or partial power-down), the internal circuitry detects the loss of supply and disables both outputs within nanoseconds, preventing back-current flow through the device.
What is the maximum capacitive load this device can drive reliably?
At VCC = 3.3 V and Tamb = 25 °C, the device maintains specified VOH/VOL with CL ≤ 50 pF and output frequency ≤ 10 MHz. For heavier loads (>50 pF), propagation delay increases linearly; derating curves in the datasheet show tpd increases by ~0.1 ns/pF beyond 30 pF at VCC = 3.3 V.
Is the VSSOP8 package (SOT765-1) compatible with standard reflow profiles?
Yes. The SOT765-1 package is qualified for IPC/JEDEC J-STD-020D moisture sensitivity level 1 (MSL-1) and supports standard lead-free reflow profiles with peak temperatures up to 260 °C. Its 0.5 mm lead pitch and 2.3 mm body width are compatible with automated optical inspection and AOI-based solder joint verification.
74LVC2G86DC,125 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- XOR (Exclusive OR)
- Number of Circuits:
- 2
- Number of Inputs:
- 2
- Features:
- -
- Voltage - Supply:
- 1.65V ~ 5.5V
- Current - Quiescent (Max):
- 4 µA
- Current - Output High, Low:
- 32mA, 32mA
- Input Logic Level - Low:
- 0.58V ~ 1.65V
- Input Logic Level - High:
- 1.07V ~ 3.85V
- Max Propagation Delay @ V, Max CL:
- 3.6ns @ 5V, 50pF
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSSOP
74LVC2G86DC,125 FAQ
1.How can I place an order for 74LVC2G86DC,125 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC2G86DC,125 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC2G86DC,125 reliable?
The price and inventory of 74LVC2G86DC,125 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC2G86DC,125 is usually 5 days.
3.What payment methods are accepted for 74LVC2G86DC,125?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC2G86DC,125 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC2G86DC,125?
74LVC2G86DC,125 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC2G86DC,125 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC2G86DC,125?
For technical support, including 74LVC2G86DC,125 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC2G86DC,125 requirements.
6.How does Aetrix verify that 74LVC2G86DC,125 is sourced from the original manufacturer or authorized distributors?
All 74LVC2G86DC,125 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC2G86DC,125 meets industry standards.
7.What is the process for return or replacement of 74LVC2G86DC,125?
All 74LVC2G86DC,125 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC2G86DC,125, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC2G86DC,125 part is unused and in its original packaging.
Return procedure for 74LVC2G86DC,125:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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