Nexperia USA Inc. 74LVC2G86GT,115

Overview

74LVC2G86GT,115 from Nexperia is a dual 2-input EXCLUSIVE-OR gate in XSON8 package (SOT833-1), operating from 1.65 V to 5.5 V supply, featuring Schmitt-trigger inputs for noise immunity, IOFF partial power-down protection, and 5.5 V overvoltage-tolerant inputs enabling mixed-voltage level translation between 3.3 V and 5 V systems - used in digital logic interfacing, bus arbitration, and parity generation circuits.

For engineers reviewing the 74LVC2G86GT,115 datasheet, 74LVC2G86GT,115 pinout, 74LVC2G86GT,115 application, or 74LVC2G86GT,115 equivalent, key selection criteria include its dual XOR function with guaranteed propagation delay ≤4.5 ns at 5.5 V, ±24 mA output drive at 3.0 V, -40 °C to +125 °C temperature range, and IOFF-enabled safe power sequencing in hot-swap or partial-power-down systems.

Technical Context

This device implements two independent CMOS XOR gates with Schmitt-trigger input thresholds, enabling robust operation with slow-rising or noisy signals. Each gate accepts inputs up to 5.5 V regardless of VCC, supporting bidirectional voltage translation without external components.

The IOFF circuit actively disables outputs when VCC = 0 V, limiting backflow current to ±2 μA and preventing damage during power sequencing. It complies with JEDEC standards JESD8-7, JESD8-5, JESD8C, and JESD36 across its full 1.65–5.5 V supply range.

Key Specifications

Pinout & Package

XSON8 plastic extremely thin small outline package (SOT833-1); no leads; 8 terminals; body dimensions 1.0 mm × 1.95 mm × 0.5 mm; thermal pad absent; pin 1 indicator located on lower left corner below marking code "V86".

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual XOR gate applications.

Compared with SN74LVC2G86DBVR and 74AUP2G86GS,132, the 74LVC2G86GT,115 uniquely balances high-speed performance (≤4.5 ns), industry-leading density (XSON8, 1.0×1.95 mm), and robust 5.5 V input tolerance - making it optimal for space-constrained, mixed-voltage, and thermally demanding applications where timing predictability and IOFF safety are critical.

Availability

74LVC2G86GT,115 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, USB-C port controller logic, automotive body control modules, and medical sensor interface hubs requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for 74LVC2G86GT,115 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Nexperia is a global semiconductor expert delivering high-performance logic, discrete, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in industrial, automotive, and consumer electronics.

The 74LVC2G86GT,115 belongs to Nexperia's LVC logic family - engineered for low-voltage operation, mixed-signal interoperability, and robustness in harsh environments, with emphasis on signal integrity, power sequencing safety, and high-density packaging.

FAQ

Does the 74LVC2G86GT,115 support true bidirectional level translation?

No - it supports unidirectional voltage translation only. Inputs tolerate up to 5.5 V regardless of VCC, allowing 5 V signals to drive a 1.8 V–3.3 V powered device, but outputs swing only between GND and the applied VCC. For true bidirectional translation, a dedicated level shifter IC is required.

What is the maximum capacitive load the 74LVC2G86GT,115 can drive while maintaining specified tpd?

The datasheet specifies dynamic characteristics with CL = 30 pF (for VCC ≤ 2.7 V) and CL = 50 pF (for VCC ≥ 3.0 V). Propagation delay increases linearly with load capacitance; at CL = 100 pF and VCC = 3.3 V, tpd degrades by ~30% versus the 50 pF test condition, remaining within functional timing margins for most non-critical paths.

Can the 74LVC2G86GT,115 be operated with VCC = 0 V while inputs remain at 3.3 V?

Yes - the IOFF feature ensures outputs are high-impedance and leakage remains ≤±2 μA when VCC = 0 V, even with inputs held at 3.3 V. This is validated per JEDEC JESD78 and allows safe "live" signal presence during power-down sequences without damaging the device or upstream sources.

Is the marking code "V86" sufficient to identify the 74LVC2G86GT,115 on the physical package?

Yes - per Table 2, the marking code "V86" is assigned specifically to 74LVC2G86GT (SOT833-1), 74LVC2G86DP (TSSOP8), and 74LVC2G86DC (VSSOP8). Pin 1 location (lower left corner below marking) and package outline (1.0 × 1.95 mm XSON8) must be verified visually or with calipers to distinguish GT from DP/DC variants.