Nexperia USA Inc. 74LVC595APW,112
- Part No.:
- 74LVC595APW,112
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Shift Registers
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74LVC595APW,112.pdf
- Description:
- IC 8BIT SHIFT REGISTER 16-TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,525
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Product details
Overview
74LVC595APW,112 from Nexperia is an 8-bit serial-in/parallel-out shift register with separate shift and storage clocks, 3-state outputs, asynchronous master reset (MR), and Schmitt-trigger inputs. It operates from 1.2 V to 3.6 V, accepts 5.5 V-tolerant inputs, and supports mixed-voltage interfacing in LED matrix drivers and microcontroller GPIO expanders.
For engineers reviewing the 74LVC595APW,112 datasheet, 74LVC595APW,112 pinout, 74LVC595APW,112 application, or 74LVC595APW,112 equivalent, key selection criteria include propagation delay (≤7.7 ns at 3.6 V), IOFF-enabled partial power-down, -40 °C to +125 °C operation, and TSSOP16 package compatibility with high-density PCB layouts.
Technical Context
The device implements two independent synchronous registers: an 8-stage shift register clocked by SHCP and a storage latch clocked by STCP, enabling pipelined data transfer. MR asynchronously clears only the shift register, while OE independently controls 3-state output enable without affecting internal state.
Inputs tolerate up to 5.5 V regardless of VCC (1.2–3.6 V), allowing direct connection to 5 V logic; Schmitt-trigger thresholds ensure noise immunity on slow-rising signals, and IOFF circuitry disables outputs during power-down to prevent backflow current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 1.2 V to 3.6 V - enables single-supply operation in battery-powered and low-voltage embedded systems |
| Input Voltage Tolerance | Up to 5.5 V - permits direct interface with legacy 5 V controllers without level-shifting circuitry |
| Propagation Delay | ≤7.7 ns (VCC = 3.0–3.6 V) - supports >115 MHz clock rates for high-throughput serial-to-parallel conversion |
| Operating Temperature | -40 °C to +125 °C - qualified for automotive under-hood and industrial control environments |
| IOFF Leakage | ≤20 μA at VCC = 0 V - prevents damaging back-current when powered down in hot-swap or partial-power-down systems |
| Output Drive | ±24 mA (VCC = 3.0 V) - directly drives LEDs or logic inputs without external buffers in display and I/O expansion |
| ESD Rating | HBM >2000 V, CDM >1000 V - meets industrial robustness requirements for handling and board assembly |
Pinout & Package
TSSOP16 plastic thin shrink small outline package (SOT403-1); 16 leads; body width 4.4 mm; 0.65 mm pitch; exposed pad not electrically connected.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (Q0) | Parallel output stage 0 | LSB of 8-bit parallel output bus; driven only when OE = LOW |
| 2 (Q1) | Parallel output stage 1 | Second bit of parallel output; synchronized to STCP edge |
| 3 (Q2) | Parallel output stage 2 | Third bit of parallel output; latched from shift register on STCP↑ |
| 4 (Q3) | Parallel output stage 3 | Fourth bit of parallel output; maintains state until next STCP↑ |
| 5 (Q4) | Parallel output stage 4 | Fifth bit of parallel output; isolated from shift register after STCP↑ |
| 6 (Q5) | Parallel output stage 5 | Sixth bit of parallel output; high-impedance when OE = HIGH |
| 7 (Q6) | Parallel output stage 6 | Seventh bit of parallel output; unaffected by OE transitions |
| 8 (GND) | Ground reference | 0 V return path for all internal logic and output drivers |
| 9 (Q7S) | Serial output | MSB of shift register; cascades to DS of next device in daisy-chain |
| 10 (MR) | Master reset | Asynchronous active-LOW input that clears shift register only |
| 11 (SHCP) | Shift clock | LOW-to-HIGH edge shifts data into Q0 and advances all stages |
| 12 (STCP) | Storage clock | LOW-to-HIGH edge transfers 8-bit content from shift to storage register |
| 13 (OE) | Output enable | Active-LOW control of all 8 parallel outputs; no effect on registers |
| 14 (DS) | Serial data input | Data loaded into Q0 on first SHCP↑ after valid setup/hold timing |
| 15 (Q7) | Parallel output stage 7 | MSB of parallel output; reflects stored value after STCP↑ |
| 16 (VCC) | Supply voltage | Primary power rail; powers logic core and output drivers (1.2–3.6 V) |
Key Features
| Feature | Design Value |
|---|---|
| Separate shift/storage clocks | Enables continuous serial loading while holding stable parallel outputs - critical for glitch-free display updates |
| 5.5 V-tolerant inputs | Eliminates need for external level translators when interfacing with 5 V microcontrollers or sensors |
| IOFF partial power-down | Prevents reverse current flow during VCC ramp-down - essential for hot-plug and multi-rail systems |
| Schmitt-trigger inputs | Accepts slow or noisy clock/data edges without false triggering - improves reliability in noisy industrial environments |
| Wide temperature range | Validated operation from -40 °C to +125 °C - suitable for automotive engine control and outdoor IoT nodes |
Applications
| LED Matrix Driver | Microcontroller GPIO Expander |
|---|---|
Use Scenario: Driving 8×8 monochrome LED displays using SPI-controlled serial data streams. IC Role / Device Role / Timing Role: Serial-to-parallel converter translating MCU SPI output into simultaneous 8-bit column/row activation signals. Use Value: Reduces MCU pin count by 5 (vs. direct drive), enables daisy-chaining for larger arrays, and provides 24 mA per output for direct LED sinking. | Use Scenario: Extending digital I/O capability of resource-constrained ARM Cortex-M0+ MCUs in smart sensor nodes. IC Role / Device Role / Timing Role: Synchronous peripheral providing additional parallel output bits controlled via hardware SPI with minimal firmware overhead. Use Value: Adds 8 deterministic, low-jitter outputs without consuming MCU timers or GPIOs; supports 3-state sharing on common buses. |
| Industrial PLC Output Module | Automotive Body Control Unit |
Use Scenario: Isolating and driving 8 relay coils or solenoids in DIN-rail mounted programmable logic controllers. IC Role / Device Role / Timing Role: Level-translating interface between 3.3 V FPGA logic and 24 V DC output stages, with MR-initiated safe shutdown. Use Value: 5.5 V input tolerance allows direct FPGA connection; IOFF prevents backfeed during power sequencing; -40 °C to +125 °C rating ensures field reliability. | Use Scenario: Controlling interior lighting zones (dome, map, footwell) in vehicle cabin modules with CAN-based command inputs. IC Role / Device Role / Timing Role: Local actuator driver converting CAN message payloads into timed PWM-capable parallel outputs via microcontroller interface. Use Value: Schmitt-trigger inputs reject EMI from adjacent motors; 125 °C rating supports placement near HVAC ducts; OE enables centralized dimming control. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 8-bit serial-in/parallel-out shift register applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC595PWR | Higher VCC range (2–6 V); slower max speed (25 MHz @ 6 V); no IOFF or 5.5 V input tolerance | Limited to 5 V-only systems; unsuitable for partial power-down or mixed-voltage designs | Select when cost sensitivity outweighs voltage flexibility and industrial temp needs |
| 74LV595PW,118 | Narrower VCC range (1.0–5.5 V); no Schmitt triggers; higher ICC (100 μA typical vs. 10 μA) | Less noise-immune; higher static power; lacks IOFF protection for hot-swap use cases | Choose only if legacy LV logic family compatibility is mandatory and thermal margin is ample |
Compared with SN74HC595PWR and 74LV595PW,118, the 74LVC595APW,112 delivers superior mixed-voltage interoperability, lower dynamic power, guaranteed industrial temperature operation, and built-in power-down safety - making it optimal for modern embedded systems requiring robustness and design scalability.
Availability
74LVC595APW,112 is available at Aetrix Electronics and suitable for LED matrix drivers, microcontroller GPIO expansion, industrial PLC output modules, and automotive body control units requiring stable component supply across extended temperature ranges.
Supply support for 74LVC595APW,112 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and discrete components optimized for efficiency, reliability, and miniaturization in automotive, industrial, and consumer applications.
The 74LVC595A series targets space-constrained, low-power embedded systems needing robust serial-to-parallel conversion with mixed-voltage tolerance and fail-safe power-down behavior.
FAQ
Can 74LVC595APW,112 be used with a 5 V microcontroller SPI interface?
Yes - its inputs are overvoltage tolerant up to 5.5 V regardless of VCC (1.2–3.6 V), allowing direct connection to 5 V SPI clock, data, and latch signals without level shifters. Outputs remain compatible with 3.3 V logic when VCC = 3.3 V, and drive strength (±24 mA) supports direct LED or relay control.
What happens to the parallel outputs during power-down?
When VCC drops to 0 V, the IOFF circuitry automatically disables all outputs, limiting OFF-state leakage to ≤20 μA. This prevents backflow current into the device from other powered rails - a critical safety feature in multi-supply systems and hot-swap applications.
How does the dual-clock architecture prevent output glitches?
Separate SHCP (shift) and STCP (storage) clocks decouple serial loading from parallel output updates. Data shifts through the 8-bit register on SHCP edges, then transfers atomically to the output latches on STCP edges - eliminating intermediate states and ensuring glitch-free transitions on all Q0–Q7 lines.
Is the TSSOP16 package (SOT403-1) RoHS and REACH compliant?
Yes - Nexperia certifies the 74LVC595APW,112 as fully compliant with RoHS Directive 2011/65/EU and REACH Regulation (EC) No. 1907/2006. The SOT403-1 package uses lead-free matte tin terminations and halogen-free molding compound, with full material declarations available upon request.
74LVC595APW,112 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Shift Register
- Output Type:
- Tri-State
- Number of Elements:
- 1
- Number of Bits per Element:
- 8
- Function:
- Serial to Parallel, Serial
- Voltage - Supply:
- 1.65V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
74LVC595APW,112 FAQ
1.How can I place an order for 74LVC595APW,112 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC595APW,112 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC595APW,112 reliable?
The price and inventory of 74LVC595APW,112 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC595APW,112 is usually 5 days.
3.What payment methods are accepted for 74LVC595APW,112?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC595APW,112 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC595APW,112?
74LVC595APW,112 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC595APW,112 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC595APW,112?
For technical support, including 74LVC595APW,112 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC595APW,112 requirements.
6.How does Aetrix verify that 74LVC595APW,112 is sourced from the original manufacturer or authorized distributors?
All 74LVC595APW,112 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC595APW,112 meets industry standards.
7.What is the process for return or replacement of 74LVC595APW,112?
All 74LVC595APW,112 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC595APW,112, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC595APW,112 part is unused and in its original packaging.
Return procedure for 74LVC595APW,112:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC595APW,112 Tags
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SN74HC164DR
Texas Instruments
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SN74HC595DR
Texas Instruments

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74HC595PW,118
Nexperia USA Inc.
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SN74HC165PWR
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HEF4094BT,653
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74HC595D,118
Nexperia USA Inc.
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SN74HC595PWR
Texas Instruments

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74HC165D,653
Nexperia USA Inc.
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SN74LV165APWR
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74HC595BQ,115
Nexperia USA Inc.

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74HC165BQ,115
Nexperia USA Inc.
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CD4094BPWR
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