Nexperia USA Inc. 74LVC8T595BQX
- Part No.:
- 74LVC8T595BQX
- Manufacturer:
- Nexperia USA Inc.
- Category:
- Shift Registers
- Package:
- 20-VFQFN Exposed Pad
- Datasheet:
-
74LVC8T595BQX.pdf
- Description:
- 74LVC8T595BQ/SOT764/DHVQFN20
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LVC8T595 from Nexperia is a dual-supply 8-bit serial-in/serial-or-parallel-out shift register with independent shift and storage registers, 3-state outputs, and IOFF-enabled partial power-down operation. It supports voltage translation between 1.1 V and 5.5 V on both VCC(A) (input/control domain) and VCC(B) (output domain), enabling interoperability across 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, and 5.0 V logic nodes in industrial I/O expanders and LED driver interfaces.
For engineers reviewing the 74LVC8T595 datasheet, 74LVC8T595 pinout, 74LVC8T595 application, or 74LVC8T595 equivalent, this device is selected for level-translating serial-to-parallel data distribution where independent clocking of shift and storage registers, suspend-mode safety, and ±24 mA output drive at 3.0 V are critical design requirements.
Technical Context
The device implements two synchronized but separately clocked 8-bit registers: an upstream shift register clocked by SHCP (data shifted on rising edge) and a downstream storage register clocked by STCP (data latched on rising edge). This architecture enables pipeline staging - e.g., new serial data can be loaded while previous parallel outputs remain stable.
VCC(A) powers MR, SHCP, STCP, OE, DS, and Q7S; VCC(B) powers all eight Qn outputs and defines their voltage swing and drive strength. The IOFF circuit disables Qn outputs when VCC(A) = GND, forcing high-impedance OFF-state regardless of VCC(B) level - a key requirement for hot-swap and multi-rail system isolation.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply range (VCC(A)) | 1.1 V to 5.5 V - powers control inputs and enables level translation from ultra-low-voltage microcontrollers to higher-voltage peripherals. |
| Supply range (VCC(B)) | 1.1 V to 5.5 V - sets output voltage domain and drive capability; allows Qn outputs to interface directly with 1.2 V ASICs or 5 V displays. |
| Output drive (VCC(A)=VCC(B)=3.0 V) | ±24 mA - sufficient to directly drive LEDs or standard CMOS loads without external buffers in space-constrained designs. |
| Propagation delay (STCP→Qn, VCC=3.3 V) | 1.3 ns to 15.4 ns - ensures deterministic timing for synchronous latch operations in real-time control loops up to 130 MHz. |
| IOFF leakage (suspend mode) | <±2 μA - prevents backflow current when VCC(A) is powered down while VCC(B) remains active, protecting upstream logic. |
| Operating temperature | –40 °C to +125 °C - qualified for under-hood automotive modules and industrial motor drives requiring extended thermal margin. |
| ESD rating (HBM) | >4000 V - robust against handling and board-level transients in automated assembly and field-replaceable units. |
Pinout & Package
DHVQFN20 package (SOT764-1), 2.5 × 4.5 × 0.85 mm body, no leads, thermally enhanced, exposed die pad (GND-connected).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 10, 11, 12, 13, 20 | GND / VCC(A) | Ground reference for input domain (pins 10–13) and primary supply for control logic (pin 20); pin 1 is thermal pad (non-electrical unless soldered to GND plane). |
| 2–9 | Q0–Q7 | Parallel output terminals referenced to VCC(B); each independently 3-state controllable via OE; support simultaneous 8-bit data latching. |
| 14 | Q7S | Serial output - reflects stage-7 of shift register; referenced to VCC(A); enables daisy-chaining multiple devices. |
| 15 | MR | Master reset (active LOW) - asynchronously clears shift register only; storage register and outputs unaffected unless STCP asserted. |
| 16 | SHCP | Shift clock input - rising-edge triggered; advances serial data through shift register stages; tolerant of 5.5 V inputs. |
| 17 | STCP | Storage clock input - rising-edge triggered; transfers full 8-bit content from shift to storage register; controls parallel output update timing. |
| 18 | OE | Output enable (active LOW) - places Q0–Q7 in high-impedance state; overrides storage register contents; referenced to VCC(A). |
| 19 | DS | Serial data input - accepts 0 V to 5.5 V signals; sampled on SHCP rising edge; compatible with mixed-voltage host controllers. |
| VCC(B) (pin 19 side) | Supply B | Power rail for Q0–Q7 outputs; decoupling required near pins 1 and 19 per layout guidelines to maintain signal integrity at >100 MHz. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent supply domains | VCC(A) and VCC(B) operate from 1.1 V to 5.5 V - eliminates external level shifters in mixed-voltage systems like IoT sensor hubs interfacing 1.8 V MCUs with 3.3 V displays. |
| Separate SHCP and STCP clocks | Enables asynchronous pipelining: new serial data loads into shift register while prior data remains latched and driven on Qn outputs - critical for glitch-free display refresh or LED scanning. |
| IOFF partial power-down | When VCC(A) = GND, Qn outputs enter guaranteed high-Z state even if VCC(B) is active - prevents bus contention during firmware updates or sleep/wake transitions. |
| ±24 mA output drive @ 3.0 V | Drives 8× LEDs directly (e.g., 5 mA per segment) or fan-outs to 10+ standard CMOS inputs without buffering - reduces BOM count in compact PCBs. |
| Suspend mode (VCC(A) = GND) | Zero static current draw from VCC(A) domain; Qn outputs forced to high-Z regardless of OE or STCP state - simplifies power sequencing in multi-rail FPGA carrier boards. |
Applications
| LED Matrix Driver | Industrial I/O Expander |
|---|---|
|
Use Scenario: Driving 8×8 monochrome LED matrix with row/column multiplexing in embedded HMI panels. IC Role / Device Role / Timing Role: Serial-to-parallel converter that latches column data on STCP while SHCP shifts next row data - enabling seamless frame updates without visible flicker. Use Value: Dual-supply operation allows 1.8 V MCU to control 5 V LED strings; ±24 mA drive eliminates external transistor arrays. |
Use Scenario: Adding isolated digital outputs to PLC backplanes using SPI-connected microcontrollers. IC Role / Device Role / Timing Role: Level-translating shift register buffering SPI commands into parallel 8-bit control signals for solenoid drivers or relay modules. Use Value: IOFF protection prevents backfeed into MCU during module hot-swap; 125 °C rating supports operation in enclosed control cabinets. |
| Automotive Body Controller | Test Equipment Signal Generator |
|
Use Scenario: Controlling interior lighting zones (dome, map, footwell) via CAN-linked ECU with discrete PWM dimming. IC Role / Device Role / Timing Role: Parallel-output latch synchronizing with vehicle bus timing; OE enables rapid group dimming via PWM applied to all Qn simultaneously. Use Value: –40 °C to +125 °C qualification meets AEC-Q100 Grade 1; 4 kV HBM ESD withstands manufacturing and service environments. |
Use Scenario: Generating programmable 8-bit test patterns for DUT stimulus in automated functional testers. IC Role / Device Role / Timing Role: High-speed serial loading (up to 250 MHz SHCP) followed by precise STCP-triggered parallel output assertion for setup/hold validation. Use Value: Low propagation skew (≤1.2 ns across Q0–Q7) ensures simultaneous edge alignment critical for timing margin analysis. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-supply shift register applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LV8154ARGYR | Single-supply (1.65–5.5 V), no VCC(A)/VCC(B) separation; lacks IOFF; max fSHCP = 80 MHz at 3.3 V. | Not suitable for true level translation; requires external level shifters when interfacing disparate voltage domains. | Select only when system uses uniform 3.3 V logic and IOFF is not required for power sequencing. |
| 74AVC8T245BQ | Octal bus transceiver (not shift register); bidirectional; no storage register or serial interface; supports 1.2–3.6 V. | Cannot perform serial-to-parallel conversion; limited to point-to-point voltage translation without data staging. | Choose only for simple bidirectional level shifting - not for shift-register functionality or pipeline latching. |
Compared with SN74LV8154ARGYR and 74AVC8T245BQ, the 74LVC8T595 uniquely delivers independent dual-supply operation, IOFF-enabled suspend mode, and separate shift/storage clocks - making it the sole option for robust, glitch-free serial-to-parallel translation in thermally demanding, multi-voltage embedded systems.
Availability
74LVC8T595 is available at Aetrix Electronics and suitable for industrial I/O expansion, automotive lighting control, LED matrix driving, and test equipment signal generation requiring stable component supply across extended temperature and mixed-voltage environments.
Supply support for 74LVC8T595 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions optimized for efficiency, reliability, and miniaturization in high-volume applications.
The 74LVC8T595 belongs to Nexperia's LVC logic family, engineered for low-voltage mixed-signal interfacing with emphasis on voltage translation, power-aware operation, and industrial-grade robustness.
FAQ
Can VCC(A) and VCC(B) be set to different voltages during normal operation?
Yes - the device is explicitly designed for dual-supply operation. VCC(A) may be 1.8 V (for a low-power MCU interface) while VCC(B) is 5.0 V (to drive legacy 5 V peripherals), with full functionality including 3-state control, IOFF, and timing specifications maintained across the full 1.1 V–5.5 V range for each supply.
What happens to Qn outputs when OE is HIGH and VCC(A) = GND (suspend mode)?
In suspend mode (VCC(A) = GND), all Qn outputs are forced into a guaranteed high-impedance OFF-state regardless of OE logic level, STCP state, or storage register content. This behavior is enforced by the IOFF circuit and is electrically verified per datasheet Table 6 (IOZ ≤ ±2 μA).
Is the Q7S output referenced to VCC(A) or VCC(B)?
Q7S is referenced to VCC(A), as confirmed in Section 5.2 ("Symbol Pin Description") and Figure 2 ("Functional diagram"). This allows Q7S to interface directly with the next device's DS input in daisy-chained configurations without level-shifting, provided both share the same VCC(A) domain.
Does the device support hot insertion when VCC(B) is powered before VCC(A)?
Yes - the IOFF circuit activates automatically when VCC(A) is below ~0.8 V, disabling Qn outputs and preventing back-current flow into unpowered control logic. This enables safe hot-plug operation in modular backplane systems where VCC(B) (e.g., 5 V system rail) may be present before VCC(A) (e.g., 3.3 V module controller) ramps.
74LVC8T595BQX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVC
- Package/Case:
- 20-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Shift Register
- Output Type:
- Tri-State
- Number of Elements:
- 1
- Number of Bits per Element:
- 8
- Function:
- Serial to Parallel, Serial
- Voltage - Supply:
- 1.1V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-DHVQFN (4.5x2.5)
74LVC8T595BQX FAQ
1.How can I place an order for 74LVC8T595BQX through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVC8T595BQX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVC8T595BQX reliable?
The price and inventory of 74LVC8T595BQX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVC8T595BQX is usually 5 days.
3.What payment methods are accepted for 74LVC8T595BQX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVC8T595BQX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVC8T595BQX?
74LVC8T595BQX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVC8T595BQX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVC8T595BQX?
For technical support, including 74LVC8T595BQX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVC8T595BQX requirements.
6.How does Aetrix verify that 74LVC8T595BQX is sourced from the original manufacturer or authorized distributors?
All 74LVC8T595BQX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVC8T595BQX meets industry standards.
7.What is the process for return or replacement of 74LVC8T595BQX?
All 74LVC8T595BQX units undergo pre-shipment inspection (PSI). If there is an issue with 74LVC8T595BQX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVC8T595BQX part is unused and in its original packaging.
Return procedure for 74LVC8T595BQX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVC8T595BQX Tags
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SN74HC164DR
Texas Instruments
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SN74HC595DR
Texas Instruments

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74HC595PW,118
Nexperia USA Inc.
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SN74HC165PWR
Texas Instruments

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HEF4094BT,653
Nexperia USA Inc.

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74HC595D,118
Nexperia USA Inc.
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SN74HC595PWR
Texas Instruments

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74HC165D,653
Nexperia USA Inc.
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SN74LV165APWR
Texas Instruments

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74HC595BQ,115
Nexperia USA Inc.

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74HC165BQ,115
Nexperia USA Inc.
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CD4094BPWR
Texas Instruments
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