Nexperia USA Inc. 74LVT126PW,118
- Part No.:
- 74LVT126PW,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
74LVT126PW,118.pdf
- Description:
- IC BUF NON-INVERT 3.6V 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
74LVT126PW,118 from Nexperia is a 3.3 V quad non-inverting 3-state buffer with bus-hold inputs, IOFF partial power-down protection, and ±64 mA/–32 mA output drive. It operates from 2.7 V to 3.6 V, accepts 5.5 V-tolerant inputs, and functions across –40 °C to +85 °C for mixed-voltage board interfacing in industrial control backplanes.
For engineers reviewing the 74LVT126PW,118 datasheet, 74LVT126PW,118 pinout, 74LVT126PW,118 application, or 74LVT126PW,118 equivalent, this device supports live insertion, TTL-level compatibility, high-impedance bus isolation, and robust ESD protection (HBM >2000 V, CDM >1000 V) in space-constrained TSSOP14 layouts.
Technical Context
This BiCMOS logic device implements four independent non-inverting buffers, each controlled by dedicated active-low output enable (nOE) inputs. Its IOFF circuitry disables outputs and blocks reverse current when VCC = 0 V, enabling safe partial power-down in multi-rail systems.
Bus-hold inputs eliminate external pull-ups by maintaining last-valid logic state at unused pins, while overvoltage-tolerant inputs (up to 5.5 V) allow direct interfacing with 5 V buses without level shifters. Propagation delays are as low as 1.0 ns (tPLH/tPHL @ 3.3 V), supporting high-speed data routing in synchronous digital subsystems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 2.7 V to 3.6 V - ensures stable operation across industrial-grade voltage rails and brown-out margins. |
| Input Voltage Range | 0 V to 5.5 V - enables direct connection to legacy 5 V logic without external translation circuitry. |
| Output Drive | +64 mA / –32 mA - supports driving heavy capacitive loads and fan-out to multiple CMOS/TTL inputs. |
| Propagation Delay | 1.0 ns (min) @ 3.3 V - meets timing requirements for sub-500 MHz clock-domain bridging and address/data latching. |
| IOFF Leakage | ±100 μA @ VCC = 0 V - prevents damaging backflow current during hot-swap or power sequencing events. |
| Operating Temperature | –40 °C to +85 °C - qualified for deployment in uncontrolled industrial enclosures and outdoor edge nodes. |
| ESD Protection | HBM >2000 V, CDM >1000 V - exceeds JEDEC JS-001/JS-002 Class 2/C3 for assembly-line robustness. |
Pinout & Package
TSSOP14 package (SOT402-1): 4.4 mm body width, 0.65 mm lead pitch, 14-terminal surface-mount outline optimized for automated placement and thermal dissipation in dense PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (active-low output enable) | Independent control per buffer; LOW enables output, HIGH forces high-impedance OFF-state. |
| 2, 5, 9, 12 | nA (data input) | Bus-hold enabled; retains last logic state when floating-no external pull-up required. |
| 3, 6, 8, 11 | nY (non-inverting output) | BiCMOS output stage delivers +64 mA sink / –32 mA source into 50 pF load. |
| 7 | GND | Reference ground plane connection; decoupling capacitor must be placed adjacent to Pin 7. |
| 14 | VCC | Primary supply rail; requires local 100 nF ceramic decoupling between Pins 7 and 14. |
Key Features
| Feature | Design Value |
|---|---|
| Quad 3-state buffer architecture | Four independent channels with individual OE control enable selective bus arbitration and time-multiplexed data paths. |
| IOFF partial power-down | Outputs automatically disable and block reverse current when VCC = 0 V-critical for hot-plug and modular system designs. |
| 5.5 V-tolerant inputs | Accepts 5 V logic signals while powered from 3.3 V rail-eliminates level translators in mixed-voltage backplanes. |
| Bus-hold input circuitry | Maintains valid logic state on unterminated inputs-reduces BOM count and PCB real estate for unused signal lines. |
| Live insertion support | Withstands voltage transients during board insertion into powered backplanes-enables field-replaceable module architectures. |
Applications
| Industrial Backplane Interface | Legacy System Bus Extension |
|---|---|
Use Scenario: Interfacing 3.3 V microcontroller peripherals to a 5 V ISA-style industrial backplane with shared address/data lines. IC Role / Device Role / Timing Role: Level-shifting buffer and bus isolator that enables bidirectional data flow while preventing contention during reset or sleep states. Use Value: Eliminates need for discrete level shifters and pull-up networks, reducing component count by 6+ parts per interface channel. |
Use Scenario: Adding modern FPGA-based I/O modules to aging PLC chassis using existing 5 V bus infrastructure. IC Role / Device Role / Timing Role: Signal repeater and bus driver that maintains signal integrity across long traces while providing 3-state control for slot arbitration. Use Value: Enables drop-in replacement of obsolete 74ACT126 without redesigning power delivery or termination schemes. |
| Hot-Swappable Module Control | Embedded Test Access Port |
Use Scenario: Managing communication lines between a main controller and field-replaceable sensor modules inserted into powered carrier boards. IC Role / Device Role / Timing Role: Isolation gate that prevents backfeeding during module insertion/removal and enforces clean bus release via OE-controlled tri-state. Use Value: Meets IEC 61000-4-2 Level 3 ESD immunity requirements without additional TVS diodes on data lines. |
Use Scenario: Buffering JTAG/SWD debug signals between a 3.3 V SoC and test fixtures operating at 5 V logic levels. IC Role / Device Role / Timing Role: Signal conditioner that ensures setup/hold timing compliance and drives fixture capacitance up to 100 pF. Use Value: Supports 10 MHz+ JTAG clock rates with <3.9 ns propagation delay-maintains full boundary-scan visibility across production test cycles. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126APW | Lower drive (+24 mA/–24 mA), narrower VCC range (1.65 V–3.6 V), no IOFF or bus-hold. | Suitable only for 3.3 V-only systems without hot-swap or 5 V interfacing needs. | Select when cost sensitivity outweighs mixed-voltage and power-down requirements. |
| 74ALVC126PW | Same pinout, higher speed (tPD = 2.5 ns typ), but lacks IOFF and bus-hold; max VCC = 3.6 V only. | Requires external pull-ups and cannot safely operate during partial power-down sequences. | Choose only for pure 3.3 V, high-frequency clock distribution where leakage and isolation are non-critical. |
Compared with SN74LVC126APW and 74ALVC126PW, the 74LVT126PW,118 uniquely combines 5.5 V input tolerance, IOFF protection, and bus-hold-making it the sole option for robust mixed-voltage backplane interfaces requiring live insertion and partial power-down compliance.
Availability
74LVT126PW,118 is available at Aetrix Electronics and suitable for industrial backplane interfaces, legacy bus extensions, hot-swappable module control, and embedded test access ports requiring stable component supply across extended temperature ranges and long product lifecycles.
Supply support for 74LVT126PW,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert focused on high-volume, high-reliability logic, analog, and MOSFET solutions for industrial, automotive, and consumer markets.
The 74LVT series targets high-speed, mixed-voltage digital interfacing applications-designed specifically for robust bus buffering, level translation, and hot-plug-capable system architectures.
FAQ
Does 74LVT126PW,118 support live insertion into a powered 5 V backplane?
Yes. Its 5.5 V-tolerant inputs, IOFF circuitry, and bus-hold functionality allow safe insertion while the backplane remains energized. The device prevents backfeeding current when VCC is unpowered, and its HBM >2000 V ESD rating withstands contact discharge during mating.
Can 74LVT126PW,118 drive a 50 pF load at 10 MHz without signal degradation?
Yes. With tPLH/tPHL ≤ 3.9 ns (max) at 3.3 V and output drive of +64 mA/–32 mA, it maintains clean edges into 50 pF loads at frequencies up to 250 MHz. Table 9 confirms stable switching with CL = 50 pF and RL = 500 Ω under recommended conditions.
What is the purpose of the bus-hold feature, and how does it affect unused inputs?
Bus-hold circuitry actively maintains the last-valid logic state on unterminated inputs using weak feedback transistors. For unused inputs, this eliminates external pull-up/pull-down resistors-reducing BOM cost and PCB area while preventing floating-node metastability in noisy industrial environments.
Is 74LVT126PW,118 pin-compatible with older 74LVT126 variants in SO14 or DHVQFN packages?
Yes. All 74LVT126 variants-including SO14 (SOT108-1), TSSOP14 (SOT402-1), and DHVQFN14 (SOT762-1)-share identical pin numbering and logic function. Only package dimensions and thermal characteristics differ; no schematic or layout changes are needed when migrating to the TSSOP14 variant.
74LVT126PW,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74LVT
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 64mA
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
74LVT126PW,118 FAQ
1.How can I place an order for 74LVT126PW,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVT126PW,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVT126PW,118 reliable?
The price and inventory of 74LVT126PW,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVT126PW,118 is usually 5 days.
3.What payment methods are accepted for 74LVT126PW,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVT126PW,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVT126PW,118?
74LVT126PW,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVT126PW,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVT126PW,118?
For technical support, including 74LVT126PW,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVT126PW,118 requirements.
6.How does Aetrix verify that 74LVT126PW,118 is sourced from the original manufacturer or authorized distributors?
All 74LVT126PW,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVT126PW,118 meets industry standards.
7.What is the process for return or replacement of 74LVT126PW,118?
All 74LVT126PW,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74LVT126PW,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVT126PW,118 part is unused and in its original packaging.
Return procedure for 74LVT126PW,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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