onsemi 74LVX04M
- Part No.:
- 74LVX04M
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74LVX04M.pdf
- Description:
- IC INVERTER 6CH 1-INP 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,978
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74LVX04M from onsemi is a low-voltage hex inverter IC with six independent CMOS inverters, designed for 3.3 V logic systems interfacing with 5 V inputs. It operates from 2.0 V to 3.6 V supply, tolerates input voltages up to 6.5 V, and delivers ±25 mA output drive at 3.3 V - enabling robust level translation in mixed-voltage digital control circuits.
For engineers reviewing the 74LVX04M datasheet, pinout, applications, or equivalent options, key selection criteria include its 3.3 V supply compatibility, 5 V-tolerant inputs, simultaneous switching noise immunity, TSSOP-14 package footprint, and guaranteed dynamic threshold performance across −40 °C to +85 °C.
Technical Context
The 74LVX04M implements six independent CMOS inverter stages with rail-to-rail input voltage tolerance (−0.5 V to +6.5 V), allowing direct connection to legacy 5 V logic without external level shifters. Its propagation delay is 4.1 ns typical (CL = 15 pF, VCC = 3.3 V) and skew between outputs is ≤1.5 ns.
It features guaranteed simultaneous switching noise limits and dynamic VIH/VIL thresholds (2.0 V/0.8 V at VCC = 3.0 V), ensuring reliable operation in high-density PCB layouts. Quiescent ICC is ≤2.0 µA at VCC = 3.6 V, supporting ultra-low-power standby modes in battery-backed systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.0 V to 3.6 V - supports standard 3.3 V I/O rails with margin for supply variation |
| Input Voltage Tolerance | −0.5 V to +6.5 V - enables safe 5 V signal injection into 3.3 V system without clamping diodes |
| Output Drive | ±25 mA - sufficient to drive multiple 74LVC inputs or small capacitive loads (≤50 pF) |
| Propagation Delay | 4.1 ns typ (CL = 15 pF, VCC = 3.3 V) - suitable for ≤100 MHz clock distribution or control signal inversion |
| Operating Temperature | −40 °C to +85 °C - qualified for industrial-grade embedded control and communications equipment |
| Input Capacitance | 4 pF typ - minimizes loading on upstream drivers and preserves signal edge integrity |
| Power Dissipation Cap | 18 pF - used to calculate dynamic ICC = CPD × VCC × fIN × (ICC/6 per gate) |
Pinout & Package
TSSOP-14 wide-body (Case 948G), 0.65 mm pitch, Pb-free and halide-free. Body dimensions: 5.0 mm × 4.4 mm × 1.2 mm max height.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 3, 5, 9, 11, 13 | A0–A5 (Inputs) | CMOS-compatible inputs accepting −0.5 V to 6.5 V; internally pulled neither - must be externally terminated |
| 2, 4, 6, 10, 12, 14 | O0–O5 (Outputs) | Inverted outputs sourcing/sinking ±25 mA; rail-to-rail swing (0 V to VCC) |
| 7 | GND | Ground reference for all logic and power domains; requires low-impedance PCB plane connection |
| 14 | VCC | Primary 2.0–3.6 V supply; decoupling capacitor (0.1 µF ceramic) required within 5 mm |
Key Features
| Feature | Design Value |
|---|---|
| 5 V-tolerant inputs | Enables direct interface between 5 V microcontrollers and 3.3 V FPGA I/O banks without external translators |
| Guaranteed dynamic VIH/VIL | Ensures noise-immune switching at 3.3 V supply even under fast edge rates (≤100 ns/V) |
| Simultaneous switching noise control | Validated VOLP/VOLV limits (±0.5 V at CL = 50 pF) prevent false triggering during bus-wide transitions |
| Pb-free and halide-free packaging | Meets RoHS 2011/65/EU and JEDEC J-STD-020 reflow profile requirements for lead-free assembly |
Applications
| Industrial PLC I/O Modules | Automotive Body Control Units |
|---|---|
Use Scenario: Inverting enable signals for isolated relay drivers and optocoupled sensor inputs in modular I/O racks. IC Role / Device Role / Timing Role: Signal-level translator and buffer, converting 5 V field-side logic to 3.3 V controller-side logic while suppressing ground bounce. Use Value: Eliminates need for discrete resistor-divider networks or dedicated level translators, reducing BOM count and layout area by >40%. | Use Scenario: Inverting wake-up signals and status flags between 5 V CAN transceivers and 3.3 V microcontroller GPIOs in door module ECUs. IC Role / Device Role / Timing Role: Bidirectional voltage-domain isolator for control path signals, with guaranteed timing skew <1.5 ns across all six channels. Use Value: Maintains deterministic signal timing across multi-channel wake-up detection, avoiding race conditions during cold-start sequences. |
| Medical Diagnostic Instrumentation | Network Equipment Management Cards |
Use Scenario: Inverting reset and interrupt lines between 5 V analog front-end ASICs and 3.3 V ARM-based management processors. IC Role / Device Role / Timing Role: High-noise-margin logic inverter with controlled edge rates, placed adjacent to mixed-signal sections. Use Value: Prevents false resets caused by ESD-induced transients on shared backplane lines, validated to IEC 61000-4-2 Level 4. | Use Scenario: Inverting LED driver enable signals and fan control PWM polarity in hot-swap power management subsystems. IC Role / Device Role / Timing Role: Low-quiescent-current inverter (≤2.0 µA) providing active-low control logic for thermal management peripherals. Use Value: Reduces standby current consumption by 85% compared to standard 74HC04 in always-on monitoring paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex inverter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74LVC04PW | Lower VCC min (1.65 V), no 5 V input tolerance - requires external clamping for 5 V inputs | Suitable only in pure 1.8–3.3 V systems; not drop-in for mixed-voltage designs | Select when full 5 V tolerance is unnecessary and lowest possible static power is critical |
| SN74AHC04DR | Wider VCC range (2–5.5 V), but VI max = VCC + 0.5 V - cannot accept 5 V inputs at 3.3 V supply | Requires redesign of input protection network if replacing 74LVX04M in 5 V–to–3.3 V interfaces | Prefer when operating at 5 V supply or when higher speed (tPD = 3.5 ns) justifies added protection circuitry |
Compared with 74LVC04PW and SN74AHC04DR, the 74LVX04M uniquely combines 5 V input tolerance with 3.3 V supply operation and guaranteed noise immunity - making it the only option requiring zero external components for legacy 5 V signal integration into modern low-voltage controllers.
Availability
74LVX04M is available at Aetrix Electronics and suitable for industrial PLC I/O modules, automotive body control units, and medical diagnostic instrumentation requiring stable component supply and long-term lifecycle support.
Supply support for 74LVX04M includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
onsemi (formerly ON Semiconductor) is a global semiconductor supplier focused on energy-efficient electronics, delivering silicon solutions for automotive, industrial, cloud, and IoT applications.
The LVX logic family, including the 74LVX04M, was engineered specifically for low-voltage, mixed-signal system interfacing - prioritizing voltage translation, noise immunity, and industrial temperature reliability over raw speed.
FAQ
What is the maximum input voltage the 74LVX04M can safely accept?
The 74LVX04M accepts DC input voltages from −0.5 V to +6.5 V regardless of VCC setting. This allows direct connection of 5 V logic signals to its inputs while powered from 3.3 V, eliminating external level-shifting components. Operation outside this range risks permanent damage per the Absolute Maximum Ratings table in the onsemi datasheet.
Does the 74LVX04M require pull-up or pull-down resistors on unused inputs?
Yes - per the Recommended Operating Conditions note, all unused inputs of the 74LVX04M must be externally held HIGH or LOW; floating inputs are prohibited. Uncontrolled inputs increase ICC, cause erratic output states, and may induce oscillation due to intermediate voltage levels crossing the dynamic threshold region.
What is the typical propagation delay of the 74LVX04M at 3.3 V supply?
The 74LVX04M exhibits a typical propagation delay of 4.1 ns (tPLH/tPHL) when loaded with 15 pF at VCC = 3.3 V and TA = 25 °C. Under worst-case conditions (CL = 50 pF, TA = −40 °C to +85 °C), the maximum delay is 11.0 ns - verified in the AC Electrical Characteristics table of the official onsemi datasheet.
Is the 74LVX04M compatible with standard TSSOP-14 footprints?
Yes - the 74LVX04M uses the TSSOP-14 wide-body package (Case 948G) with 0.65 mm pitch and defined mechanical outline per onsemi's 98ASH70246A drawing. Its soldering footprint matches IPC-7351B SOIC-14W standards, and the package is compatible with standard reflow profiles for Pb-free assembly.
How does the 74LVX04M handle simultaneous switching noise?
The 74LVX04M is characterized for simultaneous switching noise with specified VOLP (0.3 V typ) and VOLV (−0.3 V typ) limits at CL = 50 pF and VCC = 3.3 V. These values ensure that output voltage deviations remain within ±0.5 V during full-bank switching - preventing false logic transitions in adjacent sensitive circuits.
74LVX04M Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74LVX
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Inverter
- Number of Circuits:
- 6
- Number of Inputs:
- 1
- Features:
- -
- Voltage - Supply:
- 2V ~ 3.6V
- Current - Quiescent (Max):
- 2 µA
- Current - Output High, Low:
- 4mA, 4mA
- Input Logic Level - Low:
- 0.5V ~ 0.8V
- Input Logic Level - High:
- 1.5V ~ 2.4V
- Max Propagation Delay @ V, Max CL:
- 9.7ns @ 3.3V, 50pF
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
74LVX04M FAQ
1.How can I place an order for 74LVX04M through Aetrix?
Please submit a Request for Quotation (RFQ) for 74LVX04M on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74LVX04M reliable?
The price and inventory of 74LVX04M are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74LVX04M is usually 5 days.
3.What payment methods are accepted for 74LVX04M?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74LVX04M transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74LVX04M?
74LVX04M orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74LVX04M order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74LVX04M?
For technical support, including 74LVX04M datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74LVX04M requirements.
6.How does Aetrix verify that 74LVX04M is sourced from the original manufacturer or authorized distributors?
All 74LVX04M products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74LVX04M meets industry standards.
7.What is the process for return or replacement of 74LVX04M?
All 74LVX04M units undergo pre-shipment inspection (PSI). If there is an issue with 74LVX04M, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74LVX04M part is unused and in its original packaging.
Return procedure for 74LVX04M:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74LVX04M Tags
-
SN74LVC1G14DBVR
Texas Instruments
-
SN74LVC1G14DCKR
Texas Instruments
-
SN74AHC1G14DBVR
Texas Instruments
-
SN74LVC1G08DBVR
Texas Instruments
-
SN74LVC1G08DCKR
Texas Instruments
-
SN74LVC1G32DCKR
Texas Instruments
-
SN74LVC1G04DBVR
Texas Instruments
.jpg)
-
74LVC1G08GW,125
Nexperia USA Inc.
-
SN74LVC1G04DCKR
Texas Instruments
-
SN74AHC1G08DBVR
Texas Instruments
-
SN74LVC1G32DBVR
Texas Instruments
-
SN74AHCT1G08DBVR
Texas Instruments
Tech Hub
Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

