STMicroelectronics 74LX1G04STR

Overview

74LX1G04STR from STMicroelectronics is a low-voltage CMOS single inverter with 5V-tolerant inputs, operating from 1.65 V to 5.5 V supply, delivering 4.2 ns max propagation delay at 3 V, ±24 mA output drive, and 1 µA max quiescent current - used for level-shifting and signal inversion in mixed-voltage digital interfaces.

For engineers reviewing the 74LX1G04STR datasheet, 74LX1G04STR pinout, 74LX1G04STR application, or 74LX1G04STR equivalent, key selection criteria include 5V input tolerance in 3.3V systems, symmetrical 24 mA drive capability at 3V, power-down protection, balanced tPLH/tPHL delays, and SOT23-5L package compatibility with high-density PCB layouts.

Technical Context

This device implements a three-stage buffered inverter architecture using sub-micron C2MOS technology, enabling high noise immunity and stable rail-to-rail output swing across its full 1.65–5.5 V operating range. Input and output circuits feature diode-based ESD protection and power-down isolation, allowing safe operation with VCC = 0 V while accepting 0–7 V input signals.

The logic core supports data retention down to 1.2 V and guarantees truth table functionality from 1.2 V to 3.6 V. Propagation delays are tightly matched (tPLH ≅ tPHL), and output impedance is symmetrical (|IOH| = IOL ≥ 24 mA at VCC = 3 V), making it suitable for driving transmission lines and fan-out-critical nodes.

Key Specifications

Pinout & Package

SOT23-5L package: 5-pin surface-mount plastic package with 0.95 mm pitch, 2.8 × 1.5 mm footprint, and exposed pad option (not electrically connected). Pin 1 marked by notch or dot; pin 1 is N.C., pin 2 is input (1A), pin 3 is GND, pin 4 is output (1Y), pin 5 is VCC.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar single inverter applications.

Compared with SN74LVC1G04DBVR and NC7SZ04P5X, the 74LX1G04STR uniquely combines 5 V input tolerance, 4.2 ns speed at 3 V, and 1 µA max ICC - making it optimal for space-constrained, mixed-voltage industrial and automotive subsystems where robustness and timing precision are jointly critical.

Availability

74LX1G04STR is available at Aetrix Electronics and suitable for industrial sensor interfaces, USB host-level shifting, low-power IoT wake-up circuits, and legacy bus signal conditioning requiring stable component supply across extended temperature and mixed-voltage environments.

Supply support for 74LX1G04STR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer applications.

The 74LX series targets low-voltage, high-speed logic in space-constrained and power-sensitive designs - specifically engineered for reliable operation in mixed-supply systems with stringent ESD and latch-up immunity requirements.

FAQ

Can the 74LX1G04STR operate with VCC = 0 V while receiving 5 V input signals?

Yes. The device features power-down protection on both inputs and outputs, allowing 0–7 V input signals even when VCC = 0 V. This prevents back-powering and ensures safe operation during power sequencing or partial system shutdown - confirmed by absolute maximum ratings and input/output equivalent circuit diagrams in the official ST datasheet.

What is the minimum VCC required to guarantee correct logic function?

The truth table is guaranteed from 1.2 V to 3.6 V, and recommended operating VCC is 1.65 V to 5.5 V. At VCC = 1.65 V, VOH ≥ 1.2 V and VOL ≤ 0.45 V under 4 mA load, meeting standard LVCMOS thresholds. Data retention is maintained down to 1.2 V, but functional operation requires ≥1.65 V per specification tables.

Is Pin 1 (N.C.) required to be left unconnected?

Yes. Pin 1 is internally not connected and must remain unconnected or optionally tied to GND for mechanical stability - no electrical function is assigned. ST's mechanical drawings and pin description table explicitly define it as "N.C.", and connecting it to VCC or signal lines risks undefined behavior or increased parasitic coupling.

How does the 74LX1G04STR handle ESD events on its I/O pins?

All inputs and outputs integrate on-chip ESD protection diodes rated to ≥2 kV HBM. The input structure accepts −0.5 V to +7.0 V, and output clamping limits VO to −0.5 V to VCC + 0.5 V under fault conditions. These protections are verified per JEDEC JESD22-A114 and documented in the absolute maximum ratings and input/output equivalent circuit sections.