STMicroelectronics 74V1G79STR
- Part No.:
- 74V1G79STR
- Manufacturer:
- STMicroelectronics
- Category:
- Flip Flops
- Package:
- SC-74A, SOT-753
- Datasheet:
-
74V1G79STR.pdf
- Description:
- IC FF D-TYPE SNGL 1BIT SOT23-5
- Quantity:
- Payment:

- Shipping:

Inventory:4,583
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74V1G79STR from STMicroelectronics is a single positive-edge-triggered D-type flip-flop in SOT23-5L package, operating from 2V to 5.5V with 180MHz max clock frequency (at VCC = 5V), 8mA symmetrical output drive, and 1µA max quiescent current at 25°C. It enables level-sensitive data capture in portable voltage-scalable logic interfaces, such as 5V-to-3V level translation in serial control paths.
For engineers reviewing the 74V1G79STR datasheet, 74V1G79STR pinout, 74V1G79STR application, or 74V1G79STR equivalent, key selection criteria include edge-trigger timing integrity, input overvoltage tolerance (0–7V independent of VCC), propagation delay matching (tPLH ≅ tPHL), and latch-up immunity for mixed-voltage system interconnects.
Technical Context
This device implements a master-slave D flip-flop architecture triggered exclusively on the rising edge of CK, with D input sampled only during that transition. Hold time (1.0 ns min) and setup time (3.0 ns min at 5V) are specified to ensure reliable sampling under fast edge rates (dt/dv ≤ 20 ns/V at 5V).
Input protection allows 0–7V signal acceptance regardless of VCC, enabling robust interfacing between 5V, 3.3V, and 2.5V domains. Power-down protection prevents back-driving during supply-off states, and ESD-hardened I/O supports ±2kV HBM per JEDEC JESD22-A114.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2V to 5.5V - supports direct integration into battery-powered and multi-rail systems without level shifters |
| fMAX | 180MHz (typ.) at VCC = 5V - enables high-speed control sequencing in real-time digital state machines |
| tPLH / tPHL | 3.9ns / 3.9ns (typ., CL = 15pF, VCC = 5V) - balanced delays simplify timing closure in synchronous logic chains |
| IOH / IOL | –8mA / +8mA (min, VCC = 4.5V) - drives standard CMOS loads across temperature without external buffers |
| ICC (Quiescent) | 1µA (max, TA = 25°C) - minimizes standby power in always-on monitoring circuits |
| VI Input Range | –0.5V to +7.0V - accepts overvoltage inputs safely during hot-plug or supply sequencing events |
| ts / th | 3.0ns / 1.0ns (min, VCC = 5V) - defines minimum D-to-CK timing window for reliable register capture |
Pinout & Package
SOT23-5L package: 5-pin surface-mount, 1.3mm height, 2.8 × 1.5mm footprint, thermal pad not present, RoHS-compliant matte tin lead finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - D | Data Input | Asynchronous data source sampled only on CK rising edge; tolerant of 0–7V regardless of VCC |
| 2 - CK | Clock Input | Positive-edge-sensitive control signal; VIH ≥ 0.7VCC, VIL ≤ 0.3VCC, dt/dv ≤ 20 ns/V at 5V |
| 3 - GND | Ground Reference | 0V return path for all internal logic and I/O; must be low-impedance for noise immunity |
| 4 - Q | Output | True output of stored D value; symmetrical drive (±8mA), VOH/VOL specified at 4mA/8mA loads |
| 5 - VCC | Supply Voltage | Primary power rail (2–5.5V); powers internal logic and output stage; decoupling required near pin |
Key Features
| Feature | Design Value |
|---|---|
| Single D Flip-Flop | One-bit edge-triggered storage element with no reset/set - ideal for compact pipeline registers |
| Input Overvoltage Tolerance | 0–7V input range independent of VCC - eliminates need for external clamping in mixed-supply interfaces |
| Power-Down Protection | Inputs remain high-impedance and non-backdriving when VCC = 0V - prevents bus contention during power sequencing |
| High Noise Immunity | VNIH = VNIL = 28% VCC (min) - rejects transient coupling in noisy industrial PCB environments |
| Latch-Up Immunity | Improved C2MOS process - withstands >200mA transient current per JEDEC JESD78 without destructive latch-up |
Applications
| USB Peripheral Control Logic | Industrial Sensor Interface |
|---|---|
Use Scenario: Synchronizing asynchronous sensor status bits into a microcontroller's USB packet buffer using a shared 48MHz clock domain. IC Role / Device Role / Timing Role: Edge-triggered data capture register aligning asynchronous GPIO reads to precise USB SOF timing boundaries. Use Value: Eliminates metastability risk with 1.0ns hold time and 3.0ns setup margin at 48MHz, while 2V–5.5V operation matches both MCU and sensor supply rails. | Use Scenario: Level-shifting 5V encoder quadrature signals to a 3.3V FPGA input bank without external resistors or translators. IC Role / Device Role / Timing Role: Voltage-tolerant D flip-flop acting as a synchronous interface bridge with deterministic propagation delay. Use Value: 0–7V input tolerance accepts full 5V encoder swing; balanced tPLH/tPHL (≤0.2ns skew) preserves quadrature phase integrity. |
| Portable Audio Codec Clock Domain Crossing | Automotive Body Control Module (BCM) Wake-Up Latch |
Use Scenario: Capturing I²S frame sync pulses from a 5V audio codec into a 3.3V SoC's low-power audio subsystem. IC Role / Device Role / Timing Role: Single-bit synchronizer isolating clock domains while maintaining pulse width fidelity for LRCLK alignment. Use Value: 1µA ICC enables always-on readiness; 180MHz fMAX exceeds I²S frame rates up to 192kHz sample rates. | Use Scenario: Latching door-open interrupt signals in a 12V automotive BCM where main MCU sleeps until wake event occurs. IC Role / Device Role / Timing Role: Low-leakage D flip-flop holding wake status across deep-sleep cycles with VCC supplied from 5V LDO. Use Value: 1µA max ICC extends battery life; –55°C to +125°C rating ensures reliability in under-hood thermal environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar D-type flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G79DBVR | Same SOT23-5L package; 1.65–5.5V VCC; 160MHz fMAX (5V); 24µA ICC (max) | Higher ICC limits use in ultra-low-power sleep retention; identical pinout and logic function | Select when TI ecosystem compatibility or AEC-Q100 qualification is required |
| NC7SZ79P5X | SOT23-5L; 1.65–5.5V; 175MHz fMAX (5V); 10µA ICC (max); lower noise immunity (VNIH = 20% VCC) | Reduced noise margin may require additional filtering in EMI-prone automotive harnesses | Prefer for cost-sensitive consumer designs where 28% VCC noise immunity is not mandatory |
Compared with SN74LVC1G79DBVR and NC7SZ79P5X, the 74V1G79STR offers superior low-power performance (1µA vs. 10–24µA) and higher noise immunity (28% vs. 20% VCC), making it optimal for battery-critical and electrically noisy applications despite slightly higher fMAX than NC7SZ79P5X.
Availability
74V1G79STR is available at Aetrix Electronics and suitable for USB peripheral control logic, industrial sensor interface, and portable audio codec clock domain crossing requiring stable component supply across commercial and extended temperature ranges.
Supply support for 74V1G79STR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, designing and manufacturing analog, digital, and mixed-signal ICs for automotive, industrial, and consumer markets.
The 74V series targets high-speed, low-voltage CMOS logic with enhanced robustness for mixed-supply system interfacing - specifically engineered for voltage translation, clock domain isolation, and portable equipment design.
FAQ
Is 74V1G79STR compatible with 1.8V logic systems?
No - the absolute minimum recommended VCC is 2.0V per STMicroelectronics' Recommended Operating Conditions. At 1.8V, VIH and VIL thresholds fall outside specification, and propagation delay increases significantly beyond AC limits. Use 74LVC1G79 or 74AUP1G79 for true 1.8V operation.
Can the 74V1G79STR drive a 50pF load at 100MHz?
Yes - AC Electrical Characteristics specify tPLH/tPHL up to 50pF load at 100MHz (fMAX = 120MHz min at VCC = 3.3V, CL = 50pF). However, output voltage margins (VOH/VOL) degrade at 8mA drive into 50pF; verify signal integrity with board-level simulation.
Does 74V1G79STR have asynchronous reset or set functionality?
No - the 74V1G79STR is a basic positive-edge D flip-flop with only D, CK, Q, VCC, and GND terminals. It lacks asynchronous or synchronous reset/set pins. For reset capability, consider ST's 74V1G80 (D-type with async reset) or 74V1G74 (dual D-type with reset).
What is the maximum input rise/fall time supported at 5V operation?
At VCC = 5.0V ± 0.5V, the maximum allowable input dt/dv is 20 ns/V per datasheet Note 1, meaning rise/fall times must be ≤100ns for a full 5V swing. Slower edges increase susceptibility to false triggering and violate guaranteed timing margins for ts/th.
74V1G79STR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- 74V
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Standard
- Type:
- D-Type
- Output Type:
- Non-Inverted
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Clock Frequency:
- 180 MHz
- Max Propagation Delay @ V, Max CL:
- 6.5ns @ 5V, 50pF
- Trigger Type:
- Positive Edge
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Current - Quiescent (Iq):
- 1 µA
- Input Capacitance:
- 4 pF
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-5
74V1G79STR FAQ
1.How can I place an order for 74V1G79STR through Aetrix?
Please submit a Request for Quotation (RFQ) for 74V1G79STR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74V1G79STR reliable?
The price and inventory of 74V1G79STR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74V1G79STR is usually 5 days.
3.What payment methods are accepted for 74V1G79STR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74V1G79STR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74V1G79STR?
74V1G79STR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74V1G79STR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74V1G79STR?
For technical support, including 74V1G79STR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74V1G79STR requirements.
6.How does Aetrix verify that 74V1G79STR is sourced from the original manufacturer or authorized distributors?
All 74V1G79STR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74V1G79STR meets industry standards.
7.What is the process for return or replacement of 74V1G79STR?
All 74V1G79STR units undergo pre-shipment inspection (PSI). If there is an issue with 74V1G79STR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74V1G79STR part is unused and in its original packaging.
Return procedure for 74V1G79STR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74V1G79STR Tags
-
SN74HC74DR
Texas Instruments

-
SN74HC74PWR
Texas Instruments

-
74LVC1G74GT,115
Nexperia USA Inc.

-
SN74LVC2G74DCUR
Texas Instruments
-
CD4013BM96
Texas Instruments

-
SN74HCT273PWR
Texas Instruments

-
SN74LVC1G74DCUR
Texas Instruments

-
SN74HC574DWR
Texas Instruments
-
74LVC1G74DC,125
Nexperia USA Inc.

-
SN74HC273DWR
Texas Instruments

-
SN74HCT574DWR
Texas Instruments

-
SN74LVC1G74DCTR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

