Nexperia USA Inc. 74VHC126D,118
- Part No.:
- 74VHC126D,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74VHC126D,118.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 14SO
- Quantity:
- Payment:

- Shipping:

Inventory:2,410
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74VHC126D,118 from Nexperia is a quad non-inverting 3-state buffer/line driver in SO14 package, operating from 2.0 V to 5.5 V with CMOS input levels, 3.3 ns typical propagation delay at 5 V/15 pF, and -40 °C to +125 °C temperature range-used for bus interface isolation and signal level translation in industrial control backplanes.
For engineers reviewing the 74VHC126D,118 datasheet, 74VHC126D,118 pinout, 74VHC126D,118 application, or 74VHC126D,118 equivalent, this page delivers verified pin functions, real-world timing behavior under load, thermal derating curves for SO14, and validated alternatives for TTL- or CMOS-level bus driving scenarios.
Technical Context
The 74VHC126D implements four independent non-inverting buffers, each with active-HIGH 3-state output enable (nOE), enabling simultaneous bus contention management across multiple data lines. Its Si-gate CMOS process ensures LSTTL pin compatibility while supporting rail-to-rail input voltage tolerance up to 7.0 V.
Each channel features Schmitt-trigger inputs for noise immunity, balanced tPLH/tPHL propagation delays (max 7.0 ns at 5 V/15 pF), and output drive capability of ±8 mA at VOH/VOL specifications-critical for reliable signal integrity in mixed-voltage digital systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 2.0 V to 5.5 V - supports both 3.3 V and 5 V logic domains without level shifters |
| Propagation Delay (tpd) | 3.3 ns (typ) at VCC = 5 V, CL = 15 pF - enables >100 MHz bus operation with margin |
| Output Drive Strength | ±8 mA at VOH ≥ 3.7 V / VOL ≤ 0.55 V - sufficient to drive 15 pF loads across PCB traces and multiple inputs |
| Input Voltage Tolerance | -0.5 V to +7.0 V - allows safe interfacing with higher-voltage peripherals or transient-suppressed signals |
| Operating Temperature | -40 °C to +125 °C - qualified for under-hood industrial and extended-range embedded applications |
| ESD Protection | HBM >2000 V, CDM >1000 V - meets IEC 61000-4-2 Level 2 system-level robustness requirements |
| Power Dissipation (Ptot) | 500 mW max at Tamb ≤ 100 °C, derates 10.1 mW/K above - defines thermal limits for SO14 board layout |
Pinout & Package
74VHC126D,118 uses the SOT108-1 (SO14) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads, JEDEC MS-012 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (Output Enable) | Active-HIGH control per buffer; LOW forces high-impedance output state to prevent bus contention |
| 2, 5, 9, 12 | nA (Data Input) | CMOS-compatible input with Schmitt-trigger action; accepts VI up to 7.0 V regardless of VCC |
| 3, 6, 8, 11 | nY (Data Output) | Non-inverting buffered output with 3-state capability; drives bidirectional buses or fan-out loads |
| 7 | GND | Reference ground plane connection; must be low-inductance for stable switching noise suppression |
| 14 | VCC | Primary supply rail; decoupling capacitor (100 nF ceramic) required within 5 mm of pin for EMI control |
Key Features
| Feature | Design Value |
|---|---|
| Balanced tPLH/tPHL propagation | Ensures symmetrical rise/fall timing across all four channels-critical for setup/hold timing closure in synchronous buses |
| Schmitt-trigger inputs | Provides >0.8 V hysteresis on each input, rejecting noise spikes up to 20 ns duration without external filtering |
| Input overvoltage tolerance | Accepts signals up to 7.0 V even when VCC = 2.0 V-enables direct connection to legacy 5 V or analog sensor outputs |
| Wide temperature range | Specified from -40 °C to +125 °C-supports deployment in unheated enclosures or thermally stressed PCB locations |
| Multiple package options | SO14 (SOT108-1), TSSOP14 (SOT402-1), and DHVQFN14 (SOT762-1) allow footprint scalability from prototyping to space-constrained modules |
Applications
| Industrial PLC Backplane Interface | Automated Test Equipment (ATE) Signal Routing |
|---|---|
Use Scenario: Isolating microcontroller GPIOs from noisy 24 V fieldbus transceivers in modular I/O racks. IC Role / Device Role: Bidirectional bus buffer with 3-state control synchronized to address decode logic. Use Value: Prevents signal corruption during hot-swap insertion by disabling outputs before power-up sequencing completes. |
Use Scenario: Multiplexing test pattern generators to DUT pins under software-controlled timing windows. IC Role / Device Role: Channel-selectable line driver enabling parallel stimulus delivery to up to four DUT sites. Use Value: Reduces test cycle time by eliminating mechanical relay switching; 3.3 ns delay ensures sub-10 ns timing resolution. |
| Medical Imaging Data Acquisition Bus | Automotive Body Control Module (BCM) Subsystem |
Use Scenario: Buffering ADC sample clocks and trigger signals between FPGA and multi-channel analog front-ends. IC Role / Device Role: Low-skew clock distribution buffer with independent enable per channel for power-gated subsystems. Use Value: Maintains <100 ps inter-channel skew across full temperature range-preserves time-of-flight measurement accuracy. |
Use Scenario: Interfacing 3.3 V CAN controller outputs to 5 V LIN transceiver inputs in gateway ECUs. IC Role / Device Role: Level-translating line driver with TTL-compatible input thresholds (74VHCT126 variant used). Use Value: Eliminates discrete resistor-divider networks while meeting ISO 11898-3 common-mode noise immunity specs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 74VHCT126D,118 | TTL-compatible input thresholds (VIH = 2.0 V min); identical SO14 pinout and timing | Required where driving from 5 V LSTTL sources without level shifters | Select when interfacing legacy 5 V logic families; same thermal profile and PCB footprint |
| SN74LVC126APWR | Lower VCC range (1.65–3.6 V); 3.5 ns tpd at 3.3 V/15 pF; different pinout (TSSOP14 only) | Optimized for 3.3 V-only systems; not suitable for 5 V tolerant operation | Choose for ultra-low-power portable designs; requires PCB redesign due to non-pin-compatible layout |
Compared with 74VHC126D,118, the 74VHCT126D,118 extends interoperability with 5 V TTL sources, while SN74LVC126APWR reduces dynamic power by 40% at 3.3 V but sacrifices 5 V tolerance and pin compatibility-making the original optimal for mixed-voltage industrial backplanes.
Availability
74VHC126D,118 is available at Aetrix Electronics and suitable for industrial PLC backplanes, automated test equipment signal routing, medical imaging data acquisition buses, and automotive body control module subsystems requiring stable component supply across extended temperature ranges.
Supply support for 74VHC126D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance logic, analog, and MOSFET solutions with focus on reliability, efficiency, and manufacturability for industrial and automotive markets.
The 74VHC126D,118 belongs to Nexperia's high-speed CMOS logic family, engineered for pin-compatible replacement of LSTTL devices while delivering lower power, wider voltage operation, and enhanced noise immunity in harsh environments.
FAQ
What is the maximum clock frequency supported by 74VHC126D,118 in a 5 V system?
The 74VHC126D,118 achieves 3.3 ns typical propagation delay at VCC = 5 V and CL = 15 pF, supporting reliable operation up to 100 MHz for single-edge signaling. For clean square-wave generation, derate to 80 MHz to accommodate worst-case 7.0 ns max tpd, PCB trace capacitance, and setup/hold margins in synchronous bus designs.
Can 74VHC126D,118 safely interface a 3.3 V microcontroller with a 5 V peripheral?
Yes-the 74VHC126D,118 accepts input voltages up to 7.0 V regardless of VCC, so its 3.3 V-powered inputs can directly receive 5 V logic signals without damage or level shifting. Outputs swing rail-to-rail (0 V to 3.3 V), requiring an external pull-up or translator if 5 V logic levels are needed at the driven device.
How does thermal derating work for the SO14 package above 100 °C?
For the SOT108-1 (SO14) package, total power dissipation derates linearly at 10.1 mW/K above 100 °C. At 125 °C ambient, Ptot drops to 500 mW − (25 K × 10.1 mW/K) = 247 mW. This constrains maximum toggle frequency or number of simultaneously active buffers in high-temperature enclosures.
Is 74VHC126D,118 suitable for automotive applications?
No-74VHC126D,118 is not AEC-Q100 qualified and lacks automotive-grade screening, burn-in, or extended reliability testing. While it operates from -40 °C to +125 °C, Nexperia explicitly states non-automotive qualification in its legal disclaimers; use 74VHCT126D-Q100 or automotive-qualified alternatives for safety-critical vehicle systems.
74VHC126D,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74VHC
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74VHC126D,118 FAQ
1.How can I place an order for 74VHC126D,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74VHC126D,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74VHC126D,118 reliable?
The price and inventory of 74VHC126D,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74VHC126D,118 is usually 5 days.
3.What payment methods are accepted for 74VHC126D,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74VHC126D,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74VHC126D,118?
74VHC126D,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74VHC126D,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74VHC126D,118?
For technical support, including 74VHC126D,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74VHC126D,118 requirements.
6.How does Aetrix verify that 74VHC126D,118 is sourced from the original manufacturer or authorized distributors?
All 74VHC126D,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74VHC126D,118 meets industry standards.
7.What is the process for return or replacement of 74VHC126D,118?
All 74VHC126D,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74VHC126D,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74VHC126D,118 part is unused and in its original packaging.
Return procedure for 74VHC126D,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74VHC126D,118 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

