STMicroelectronics 74VHCT126AMTR
- Part No.:
- 74VHCT126AMTR
- Manufacturer:
- STMicroelectronics
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74VHCT126AMTR.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 14SO
- Quantity:
- Payment:

- Shipping:

Inventory:1,340
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74VHCT126AMTR from STMicroelectronics is a quad 3-state bus buffer with TTL-compatible inputs, designed for bidirectional data routing in 5V digital systems. It features 3.8 ns typical propagation delay, ±8 mA symmetrical output drive, 2 µA max quiescent current at 25°C, and operates across 4.5–5.5 V supply. Used in address/data bus isolation on industrial control backplanes.
For engineers reviewing the 74VHCT126AMTR datasheet, 74VHCT126AMTR pinout, 74VHCT126AMTR application, or 74VHCT126AMTR equivalent, key selection criteria include 3-state enable timing (tPZL/tPHZ ≤ 8.8 ns), input voltage tolerance up to 7 V independent of VCC, and ESD immunity of 2 kV per IEC 61000-4-2.
Technical Context
This device implements four independent non-inverting buffers, each controlled by a dedicated active-low 3-state enable (G) input. All inputs accept 0–7 V regardless of VCC, enabling robust level-shifting between 5 V and 3 V domains without external circuitry.
Its C2MOS fabrication ensures latch-up immunity per JEDEC JESD78, while symmetrical |IOH| = |IOL| ≥ 8 mA supports matched rise/fall times and balanced bus loading. Power-down protection clamps inputs/outputs during VCC = 0, preventing back-driving in partial-power-down scenarios.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| tPD (typ) | 3.8 ns at VCC = 5 V, CL = 15 pF - enables sub-10 ns bus cycle timing in high-speed microcontroller interfaces |
| VCC range | 4.5–5.5 V - compatible with regulated 5 V rails and tolerates ±10% supply variation |
| IOH/IOL (min) | ±8 mA - drives standard TTL loads and sustains signal integrity across 15 cm PCB traces |
| VIH/VIL thresholds | 2.0 V / 0.8 V - guarantees reliable recognition of TTL logic levels at 5 V supply |
| ICC (max) | 2 µA at TA = 25°C - minimizes standby power in battery-backed or energy-sensitive modules |
| VOLP (max) | 0.8 V - limits ground bounce noise during simultaneous output switching |
| ESD immunity | 2 kV HBM - meets industrial handling requirements without additional protection circuitry |
Pinout & Package
74VHCT126AMTR is housed in a 14-pin TSSOP (Thin Shrink Small Outline Package) with 0.65 mm pitch, measuring 5.0 × 6.4 × 1.05 mm (D × E × A2). The package supports automated SMT assembly and provides thermal performance suitable for continuous operation at 125°C ambient.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | G1–G4 (Active-Low OE) | Independent 3-state enables per buffer; low = output enabled, high = high-Z |
| 2, 5, 9, 12 | A1–A4 (Data Inputs) | TTL-compatible inputs accepting 0–7 V; no VCC dependency for logic recognition |
| 3, 6, 8, 11 | Y1–Y4 (Data Outputs) | Non-inverting buffered outputs with ±8 mA drive and power-down clamping |
| 7 | GND | Reference ground for all I/O and internal logic; decoupling capacitor required adjacent to pin |
| 14 | VCC | Positive supply (4.5–5.5 V); internal clamp diodes protect against overvoltage transients |
Key Features
| Feature | Design Value |
|---|---|
| Input voltage tolerance | 0–7 V independent of VCC - eliminates need for external level shifters when interfacing to 3 V controllers |
| Power-down protection | Clamped I/O during VCC = 0 - prevents back-current flow into powered subsystems during hot-swap or partial power-down |
| Balanced propagation delays | tPLH ≈ tPHL - ensures minimal skew between rising/falling edges on shared buses |
| Latch-up immunity | Complies with JEDEC JESD78 Class II - withstands >100 mA injected current without destructive latch-up |
| Low dynamic noise | VOLP ≤ 0.8 V at CL = 50 pF - reduces simultaneous switching noise in dense memory or peripheral interfaces |
Applications
| Industrial PLC Backplane | Automotive Body Control Module |
|---|---|
Use Scenario: Isolating CPU address/data buses from modular I/O expansion slots in programmable logic controllers. IC Role / Device Role / Timing Role: Quad 3-state buffer providing direction-controlled bus segmentation with <8.8 ns disable time to prevent bus contention during slot reconfiguration. Use Value: Enables hot-plug capability of I/O cards by maintaining high-Z state during insertion/removal, eliminating bus glitches. | Use Scenario: Level-shifting and buffering sensor data lines (e.g., door lock status, window position) between 3.3 V MCU and 5 V analog front-end circuits. IC Role / Device Role / Timing Role: Voltage-tolerant input buffer translating TTL-level signals across supply domains while suppressing ESD events from vehicle harnesses. Use Value: Eliminates discrete Zener clamps and pull-ups, reducing BOM count and PCB area in space-constrained BCM modules. |
| Medical Diagnostic Interface | Test Equipment Signal Routing |
Use Scenario: Routing serial configuration commands from a 5 V FPGA to multiple isolated 3 V ADC/DAC channels in portable ultrasound front-ends. IC Role / Device Role / Timing Role: Non-inverting 3-state gate ensuring clean command delivery with <3.8 ns delay and <0.55 V VOL at 8 mA load. Use Value: Guarantees setup/hold timing margins for SPI clock rates up to 25 MHz without added delay compensation. | Use Scenario: Multiplexing DUT (device under test) signals onto shared test instrumentation channels in automated bench systems. IC Role / Device Role / Timing Role: Bidirectional bus isolator with independent enable controls allowing dynamic reconfiguration of signal paths during test sequences. Use Value: Reduces test fixture wiring complexity and enables software-defined channel mapping without hardware changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74VHCT126PW | Same VHCT family, identical AC/DC specs, but in 14-pin TSSOP with different moisture sensitivity level (MSL3 vs MSL1) | No functional difference; SN74VHCT126PW has TI-specific tape-and-reel packaging and RoHS marking | Select if sourcing from TI-authorized distributors or requiring TI's quality documentation traceability |
| 74LCX126MTCX | Lower VCC range (2.0–3.6 V), higher speed (tPD = 2.5 ns), but not 5 V tolerant - inputs fail above 3.6 V | Only suitable for pure 3.3 V systems; cannot replace 74VHCT126AMTR in mixed-voltage 5 V environments | Choose only for new 3.3 V designs where 5 V tolerance is unnecessary and lower propagation delay is critical |
Compared with SN74VHCT126PW and 74LCX126MTCX, the 74VHCT126AMTR uniquely supports 0–7 V input tolerance at 5 V operation, making it irreplaceable in legacy 5 V systems requiring robust hot-swap and level-shifting without redesign.
Availability
74VHCT126AMTR is available at Aetrix Electronics and suitable for industrial PLC backplanes, automotive body control modules, medical diagnostic interfaces, and test equipment signal routing requiring stable component supply and long-term lifecycle support.
Supply support for 74VHCT126AMTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
STMicroelectronics is a global semiconductor leader headquartered in Geneva, Switzerland, specializing in automotive, industrial, and power management ICs with vertical manufacturing and broad IP portfolio.
The VHCT logic family targets high-speed, low-power 5 V digital interfacing with enhanced noise immunity and voltage tolerance - specifically engineered for industrial control, instrumentation, and legacy system upgrades.
FAQ
Can 74VHCT126AMTR operate with a 3.3 V supply?
No. The 74VHCT126AMTR is specified only for 4.5–5.5 V operation. Its input thresholds (VIH = 2.0 V min, VIL = 0.8 V max) and output drive strength are optimized for 5 V TTL compatibility. Applying 3.3 V to VCC violates recommended operating conditions and may result in undefined logic states or reduced noise margin.
What is the maximum capacitive load this device can drive reliably?
The 74VHCT126AMTR is characterized up to 50 pF load capacitance in AC specifications, with tPLH/tPHL = 5.3 ns (typ) and tPZL/tPHZ = 5.1 ns (typ) at CL = 50 pF. Driving >50 pF increases propagation and enable/disable delays nonlinearly and may exceed VOL/V OH limits at full output current; external series termination is recommended beyond this limit.
Does this part support hot-swap insertion when VCC is unpowered?
Yes. The device features power-down protection on all inputs and outputs: when VCC = 0 V, inputs accept 0–7 V without damage or back-current, and outputs remain in high-impedance state. This allows safe insertion into live backplanes where other modules remain powered, provided G inputs are held high (disabled) prior to VCC ramp-up.
How does the 2 kV ESD rating apply in system design?
The 2 kV Human Body Model (HBM) rating applies to each I/O pin individually and reflects internal protection diode robustness. It permits direct handling and board assembly without special ESD precautions but does not replace system-level IEC 61000-4-2 surge protection for external connectors exposed to user interaction or cable discharge events.
74VHCT126AMTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- STMicroelectronics
- Series:
- 74VHCT
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -55°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74VHCT126AMTR FAQ
1.How can I place an order for 74VHCT126AMTR through Aetrix?
Please submit a Request for Quotation (RFQ) for 74VHCT126AMTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74VHCT126AMTR reliable?
The price and inventory of 74VHCT126AMTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74VHCT126AMTR is usually 5 days.
3.What payment methods are accepted for 74VHCT126AMTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74VHCT126AMTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74VHCT126AMTR?
74VHCT126AMTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74VHCT126AMTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74VHCT126AMTR?
For technical support, including 74VHCT126AMTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74VHCT126AMTR requirements.
6.How does Aetrix verify that 74VHCT126AMTR is sourced from the original manufacturer or authorized distributors?
All 74VHCT126AMTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74VHCT126AMTR meets industry standards.
7.What is the process for return or replacement of 74VHCT126AMTR?
All 74VHCT126AMTR units undergo pre-shipment inspection (PSI). If there is an issue with 74VHCT126AMTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74VHCT126AMTR part is unused and in its original packaging.
Return procedure for 74VHCT126AMTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74VHCT126AMTR Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

