Nexperia USA Inc. 74VHCT126D,118
- Part No.:
- 74VHCT126D,118
- Manufacturer:
- Nexperia USA Inc.
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
74VHCT126D,118.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 14SO
- Quantity:
- Payment:

- Shipping:

Inventory:2,350
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
74VHCT126D,118 from Nexperia is a quad non-inverting 3-state buffer/line driver IC with TTL-compatible inputs, operating from 4.5 V to 5.5 V supply, featuring 3.0 ns typical propagation delay (VCC = 5 V, CL = 15 pF), ±8 mA output drive, and -40 °C to +125 °C industrial temperature range - used for bus interfacing and signal isolation in digital logic systems.
For engineers reviewing the 74VHCT126D,118 datasheet, 74VHCT126D,118 pinout, 74VHCT126D,118 application, or 74VHCT126D,118 equivalent, key selection factors include TTL-level input compatibility, 3-state enable timing (tEN = 4.7 ns typ), output drive capability under heavy capacitive loads, and SO14 package thermal performance at extended temperature.
Technical Context
This device implements four independent non-inverting buffers, each with an active-HIGH output enable (nOE) controlling high-impedance state on its corresponding nY output. All inputs feature Schmitt-trigger action for noise immunity and accept voltages up to 5.5 V regardless of VCC.
It complies with JEDEC standard No. 7-A and is pin-compatible with LSTTL, enabling direct replacement in legacy 74LS126 designs. The 74VHCT variant ensures TTL-level input thresholds (VIH = 2.0 V min, VIL = 0.8 V max at VCC = 5 V), while maintaining CMOS output characteristics and low ICC (2.0 μA typ).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage (VCC) | 4.5 V to 5.5 V - Ensures stable operation across standard 5 V rail tolerances and brown-out margins. |
| Propagation Delay (tpd) | 3.0 ns (typ) at VCC = 5 V, CL = 15 pF - Enables high-speed data routing in 100+ MHz bus applications. |
| Output Drive (IO) | ±8.0 mA - Sustains logic levels driving 15–50 pF loads without degradation across temperature. |
| Input Thresholds | VIH = 2.0 V min, VIL = 0.8 V max - Guarantees reliable recognition of standard TTL logic levels. |
| Operating Temperature | -40 °C to +125 °C - Qualified for under-hood, industrial control, and power-conversion monitoring environments. |
| ESD Protection | HBM > 2000 V, CDM > 1000 V - Provides robust handling during PCB assembly and field service. |
| Power Dissipation (Ptot) | 500 mW (SO14, Tamb ≤ 100 °C) - Supports continuous operation in compact enclosures with natural convection cooling. |
Pinout & Package
74VHCT126D,118 uses the SO14 (SOT108-1) plastic small outline package: 14-pin, 3.9 mm body width, 1.27 mm lead pitch, gull-wing leads, JEDEC MS-012 compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | nOE (Output Enable) | Active-HIGH control per channel; LOW forces associated nY into high-Z state for bus sharing. |
| 2, 5, 9, 12 | nA (Data Input) | Non-inverting input with Schmitt-trigger hysteresis; accepts 0–5.5 V, tolerant of slow-rising signals. |
| 3, 6, 8, 11 | nY (Data Output) | CMOS push-pull output; drives HIGH/LOW actively or enters high-impedance when nOE = LOW. |
| 7 | GND | Reference ground node; must be low-inductance connection to minimize switching noise coupling. |
| 14 | VCC | Primary supply rail; requires local 100 nF ceramic decoupling within 5 mm of pin for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| TTL-compatible inputs | VIH = 2.0 V min / VIL = 0.8 V max at 5 V - Enables seamless interface with legacy 74LS and microcontroller GPIOs. |
| 3-state output control | Independent active-HIGH nOE per buffer - Allows dynamic bus arbitration without external logic or pull-ups. |
| Schmitt-trigger inputs | Hysteresis ≥ 0.5 V typical - Rejects noise on slow or noisy control lines (e.g., front-panel switches, sensor outputs). |
| Wide voltage tolerance | Inputs accept up to 5.5 V regardless of VCC - Permits mixed-voltage system interfacing (e.g., 3.3 V logic driving 5 V bus). |
| High-speed performance | tpd = 3.0 ns (typ), ten = 4.7 ns (typ) - Meets timing budgets for 100+ MHz clock domains and burst-mode data transfers. |
Applications
| Industrial PLC I/O Expansion | Microcontroller Bus Isolation |
|---|---|
|
Use Scenario: Isolating MCU GPIO banks from noisy 24 V industrial fieldbus transceivers and relay drivers. IC Role / Device Role / Timing Role: Bidirectional signal conditioning and level translation between 3.3 V/5 V MCU ports and 5 V TTL-compatible peripherals. Use Value: Prevents back-driving and latch-up during hot-swap events; Schmitt inputs suppress EMI-induced glitches on long traces. |
Use Scenario: Enabling/disabling multiple peripheral devices (ADCs, DACs, EEPROMs) on a shared parallel data bus. IC Role / Device Role / Timing Role: 3-state bus driver providing controlled access to memory-mapped peripherals via dedicated nOE lines. Use Value: Eliminates need for discrete MOSFET switches; enables deterministic bus turn-around with sub-5 ns enable/disable timing. |
| Legacy TTL System Upgrade | Test Equipment Signal Routing |
|
Use Scenario: Replacing obsolete 74LS126 in aging instrumentation chassis requiring drop-in reliability and lower power. IC Role / Device Role / Timing Role: Pin- and function-compatible buffer with identical SO14 footprint and LSTTL logic thresholds. Use Value: Reduces quiescent current by >95% vs. LS family while preserving timing behavior and fanout capability. |
Use Scenario: Multiplexing calibration signals, reference voltages, and trigger pulses across multiple instrument channels. IC Role / Device Role / Timing Role: Low-skew, non-inverting repeater with independent enable control for precise signal gating. Use Value: Maintains signal integrity (VOL < 0.36 V, VOH > 3.94 V) across 50 pF test fixture loads at 10 MHz switching rates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126APWR | 3.3 V only (1.65–3.6 V); LVCMOS inputs; 3.7 ns tpd at 3.3 V | Requires level-shifting for 5 V systems; optimized for modern low-voltage FPGAs and SoCs | Select when migrating to 3.3 V infrastructure and needing lower power (ICC < 1 μA) and smaller TSSOP package. |
| 74HC126D,653 | CMOS inputs (VIH = 3.85 V min at 5 V); higher VCC max (6 V); 8 ns tpd at 5 V | Lacks TTL-level compatibility; slower but more robust against overvoltage on inputs | Select when interfacing exclusively with CMOS sources and prioritizing input ruggedness over speed or legacy compatibility. |
Compared with SN74LVC126APWR, 74VHCT126D,118 supports full 5 V operation and TTL inputs without translation; compared with 74HC126D,653, it delivers faster timing and guaranteed recognition of standard TTL logic levels - making it optimal for mixed-technology upgrades and industrial bus interfaces.
Availability
74VHCT126D,118 is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, microcontroller bus isolation, legacy TTL system upgrades, and test equipment signal routing requiring stable component supply across extended temperature ranges.
Supply support for 74VHCT126D,118 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Nexperia is a global semiconductor expert delivering high-performance, reliable logic, analog, and discrete components for automotive, industrial, and consumer applications.
The 74VHCT series targets cost-sensitive, high-reliability digital interface applications where TTL compatibility, wide temperature operation, and pin-for-pin upgrade paths are essential - especially in industrial control and legacy system modernization.
FAQ
Can 74VHCT126D,118 operate reliably at 3.3 V supply?
No. The 74VHCT126D,118 is specified only for 4.5 V to 5.5 V operation. Its TTL input thresholds (VIH = 2.0 V min) and output drive strength are characterized and guaranteed solely within that range. At 3.3 V, VIH exceeds VCC, causing undefined input behavior and potential functional failure.
What is the maximum capacitive load this device can drive while maintaining timing specs?
The datasheet guarantees timing (tpd, ten, tdis) up to 50 pF load capacitance at VCC = 4.5–5.5 V. Driving >50 pF will increase propagation and enable/disable delays nonlinearly and may violate setup/hold margins in synchronous systems - external buffering is recommended beyond this limit.
Is there a pin-compatible 74VHCT126 variant in TSSOP or QFN packages?
Yes. Nexperia offers 74VHCT126PW (TSSOP14, SOT402-1) and 74VHCT126BQ (DHVQFN14, SOT762-1), both sharing identical logic, timing, and DC specifications with the SO14 version. Package selection depends on board space, thermal requirements, and assembly capabilities.
How does the Schmitt-trigger input improve noise immunity in real-world layouts?
Schmitt-trigger inputs provide ~0.5 V hysteresis, meaning the rising threshold (VIH) is ~0.5 V higher than the falling threshold (VIL). This prevents multiple output transitions when input signals cross the logic threshold slowly or with superimposed noise - critical for long traces, unshielded cables, or electrically noisy environments like motor drives.
74VHCT126D,118 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Nexperia USA Inc.
- Series:
- 74VHCT
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
74VHCT126D,118 FAQ
1.How can I place an order for 74VHCT126D,118 through Aetrix?
Please submit a Request for Quotation (RFQ) for 74VHCT126D,118 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 74VHCT126D,118 reliable?
The price and inventory of 74VHCT126D,118 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 74VHCT126D,118 is usually 5 days.
3.What payment methods are accepted for 74VHCT126D,118?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 74VHCT126D,118 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 74VHCT126D,118?
74VHCT126D,118 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 74VHCT126D,118 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 74VHCT126D,118?
For technical support, including 74VHCT126D,118 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 74VHCT126D,118 requirements.
6.How does Aetrix verify that 74VHCT126D,118 is sourced from the original manufacturer or authorized distributors?
All 74VHCT126D,118 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 74VHCT126D,118 meets industry standards.
7.What is the process for return or replacement of 74VHCT126D,118?
All 74VHCT126D,118 units undergo pre-shipment inspection (PSI). If there is an issue with 74VHCT126D,118, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 74VHCT126D,118 part is unused and in its original packaging.
Return procedure for 74VHCT126D,118:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
74VHCT126D,118 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

