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Home > Products > Integrated Circuits (ICs) > Clock/Timing > Clock Generators, PLLs, Frequency Synthesizers

Renesas 843004AG-125LF

Name: 843004AG-125LF
Brand: Renesas
SKU: 843004AG-125LF
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: 843004AG-125LF

Manufacturer:: Renesas

Category:: Clock Generators, PLLs, Frequency Synthesizers

Package:: 24-TSSOP (0.173", 4.40mm Width)

Datasheet:: 843004AG-125LF.pdf

Description:: IC FREQ SYNTH 24TSSOP

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Product details

Overview

843004AG-125LF from Renesas Electronics (formerly IDT) is a 4-output 3.3V LVPECL frequency synthesizer optimized for Ethernet reference clock generation, featuring 125MHz output frequency, 0.58ps typical RMS phase jitter (1.875MHz–20MHz offset), VCO range of 560–680MHz, and operation across 0°C to 70°C ambient temperature.

For engineers reviewing the 843004AG-125LF datasheet, 843004AG-125LF pinout, 843004AG-125LF application, or 843004AG-125LF equivalent, key selection considerations include LVPECL output termination requirements, crystal interface configuration (25MHz, 18pF parallel resonant), PLL bypass capability via nPLL_SEL, and separate V_CC/V_CCA/V_CCO supply domains for jitter-sensitive analog core isolation.

Technical Context

The 843004AG-125LF integrates a third-generation low-phase-noise VCO with fixed M=25 divider and programmable N-divider architecture, enabling precise 125MHz synthesis from a 25MHz crystal reference. Its dual-input selection (XTAL_IN/XTAL_OUT or REF_CLK) and nXTAL_SEL control allow flexible clock source routing into the PLL path.

It implements four independent LVPECL differential output pairs (Q0/nQ0, Q1/nQ1, Q2/nQ2, Q3/nQ3), each terminated internally for 50Ω transmission lines with V_CCO−2V bias, and supports master reset (MR) and PLL enable/bypass (nPLL_SEL) via LVCMOS/LVTTL logic-level inputs with internal pulldown resistors (51kΩ typical).

Key Specifications

Parameter	Value and Actual Design Meaning
Output Frequency	125MHz nominal - meets IEEE 802.3ae 10GbE reference clock requirement with ±11MHz tolerance (112–136MHz).
RMS Phase Jitter	0.58ps typical (1.875MHz–20MHz integration band) - satisfies stringent 10GbE jitter mask without external filtering.
VCO Frequency Range	560MHz–680MHz - enables stable lock under PVT variation while supporting 125MHz × 5 multiplication from 25MHz reference.
Supply Voltages	V_CC/V_CCA/V_CCO = 3.135–3.465V - separate analog (V_CCA) and output (V_CCO) rails minimize noise coupling into PLL and outputs.
Output Skew	50ps max - ensures deterministic timing alignment across all four LVPECL output pairs for multi-lane SerDes applications.
Crystal Interface	25MHz, 18pF parallel resonant - validated with ESR ≤50Ω and shunt capacitance ≤7pF for guaranteed startup and ppm accuracy.
Operating Temperature	0°C to 70°C ambient - qualified for commercial-grade Ethernet switch/router line cards and industrial networking equipment.

Pinout & Package

843004AG-125LF is housed in a lead-free 24-pin TSSOP (G package), 4.40mm × 7.8mm × 0.925mm body, JEDEC MO-153 compliant.

Pin/Terminal	Circuit Role	Design Meaning
1, 2 (nQ1, Q1)	Differential LVPECL Output Pair	True/inverted 125MHz outputs; require 50Ω termination to V_CCO−2V for proper DC bias and signal integrity.
3, 22 (V_CCO)	LVPECL Output Supply	Dedicated 3.3V rail for output drivers - must be decoupled with 0.01µF capacitor to suppress high-frequency switching noise.
4, 5 (Q0, nQ0)	Differential LVPECL Output Pair	Primary 125MHz output pair; electrically identical to Q1/nQ1 but routed separately for board layout flexibility.
6 (MR)	Master Reset Input	LVCMOS/LVTTL active-HIGH input with internal 51kΩ pulldown - forces all Qx low / nQx high when asserted, halting output activity.
7 (nPLL_SEL)	PLL Enable/Bypass Control	LVCMOS/LVTTL input; LOW enables PLL path, HIGH bypasses PLL to route REF_CLK directly to dividers for test or failover mode.
9 (V_CCA)	Analog Core Supply	3.3V analog supply for VCO and phase detector - requires RC filter (10Ω + 10µF) to isolate digital noise from sensitive analog circuitry.
11, 18 (V_CC)	Digital Core Supply	3.3V supply for logic dividers and control circuitry - decoupled with 0.01µF capacitor per pin to maintain stable internal timing.
13, 14 (XTAL_OUT, XTAL_IN)	Crystal Oscillator Interface	Drive and sense nodes for 25MHz parallel-resonant crystal; internal load caps optimized for 18pF crystal with C1=33pF/C2=27pF external tuning.
15, 19 (V_EE)	Negative Supply Reference	Ground reference for LVPECL outputs - must be connected to system ground plane with low-inductance path to minimize common-mode noise.
16 (REF_CLK)	Single-Ended Reference Input	LVCMOS/LVTTL-compatible 25MHz input; used when bypassing crystal oscillator - accepts edge rates down to 10ns rise/fall.
17 (nXTAL_SEL)	Clock Source Selector	LVCMOS/LVTTL input; LOW selects XTAL_IN/XTAL_OUT as PLL reference, HIGH selects REF_CLK for alternative timing source.
20, 21 (nQ3, Q3)	Differential LVPECL Output Pair	Third 125MHz output pair - identical electrical specs to Q0/nQ0; supports multi-port PHY clock distribution.
23, 24 (Q2, nQ2)	Differential LVPECL Output Pair	Fourth 125MHz output pair - fully independent; enables clocking of four separate 10GbE lanes or dual 25GbE interfaces.

Key Features

Feature	Design Value
Four 3.3V LVPECL output pairs	Enables simultaneous clocking of up to four 10GbE SerDes lanes without external fanout buffers, reducing BOM count and board area.
Selectable crystal or LVCMOS reference input	Supports both precision crystal-based timing and flexible single-ended clock injection - simplifies validation and field-replaceable clock source upgrades.
0.58ps typical RMS phase jitter at 125MHz	Exceeds IEEE 802.3ae 10GbE jitter compliance margin (≤1ps) using only a 25MHz crystal, eliminating need for expensive low-jitter oscillators.
Separate V_CC, V_CCA, V_CCO supply domains	Prevents digital switching noise from degrading VCO phase noise or LVPECL output edge fidelity - critical for maintaining BER in high-speed links.
Internal 51kΩ pulldown resistors on control inputs	Eliminates need for external pull-down resistors on MR, nPLL_SEL, and nXTAL_SEL - reduces component count and improves layout robustness.

Applications

10GbE Line Cards	Multi-Port Switch ASIC Clocking
Use Scenario: Providing synchronous 125MHz reference clocks to four independent 10GBASE-R PHYs on a modular line card. IC Role / Device Role / Timing Role: Primary frequency synthesizer generating jitter-compliant Ethernet reference clocks with deterministic skew between outputs. Use Value: Enables full-rate 10GbE operation across all ports without external jitter cleaners or fanout ICs, lowering power and latency.	Use Scenario: Distributing aligned 125MHz clocks to multiple switch fabric ASICs and packet buffer controllers in a chassis-based switch. IC Role / Device Role / Timing Role: Centralized clock source with four matched LVPECL outputs ensuring sub-50ps inter-chip skew for coherent packet processing. Use Value: Eliminates timing misalignment-induced packet reordering and reduces need for complex deskew logic in high-throughput forwarding engines.
Industrial Ethernet Gateways	Test Equipment Reference Timing
Use Scenario: Generating stable 125MHz clocks for industrial PROFINET or EtherCAT PHYs operating in extended temperature environments. IC Role / Device Role / Timing Role: Temperature-stable clock generator meeting 0°C to 70°C ambient spec with minimal jitter degradation over temperature. Use Value: Ensures deterministic real-time communication performance in factory automation systems where timing predictability is safety-critical.	Use Scenario: Serving as low-jitter reference for bit error rate testers (BERTs) and high-speed oscilloscopes requiring precise 125MHz sampling clocks. IC Role / Device Role / Timing Role: Ultra-low phase noise synthesizer providing clean timing基准 for measurement instrument front-ends. Use Value: Reduces measurement uncertainty in high-speed serial compliance testing by delivering 0.58ps jitter - below instrument noise floor.

10GbE Line Cards

Multi-Port Switch ASIC Clocking

Use Scenario: Providing synchronous 125MHz reference clocks to four independent 10GBASE-R PHYs on a modular line card.

IC Role / Device Role / Timing Role: Primary frequency synthesizer generating jitter-compliant Ethernet reference clocks with deterministic skew between outputs.

Use Value: Enables full-rate 10GbE operation across all ports without external jitter cleaners or fanout ICs, lowering power and latency.

Use Scenario: Distributing aligned 125MHz clocks to multiple switch fabric ASICs and packet buffer controllers in a chassis-based switch.

IC Role / Device Role / Timing Role: Centralized clock source with four matched LVPECL outputs ensuring sub-50ps inter-chip skew for coherent packet processing.

Use Value: Eliminates timing misalignment-induced packet reordering and reduces need for complex deskew logic in high-throughput forwarding engines.

Industrial Ethernet Gateways

Test Equipment Reference Timing

Use Scenario: Generating stable 125MHz clocks for industrial PROFINET or EtherCAT PHYs operating in extended temperature environments.

IC Role / Device Role / Timing Role: Temperature-stable clock generator meeting 0°C to 70°C ambient spec with minimal jitter degradation over temperature.

Use Value: Ensures deterministic real-time communication performance in factory automation systems where timing predictability is safety-critical.

Use Scenario: Serving as low-jitter reference for bit error rate testers (BERTs) and high-speed oscilloscopes requiring precise 125MHz sampling clocks.

IC Role / Device Role / Timing Role: Ultra-low phase noise synthesizer providing clean timing基准 for measurement instrument front-ends.

Use Value: Reduces measurement uncertainty in high-speed serial compliance testing by delivering 0.58ps jitter - below instrument noise floor.

Equivalent & Alternatives

The following parts are listed as comparable options for similar frequency synthesizer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
Si5338A-A-GM	Programmable I2C-configurable synthesizer with wider output frequency range (0.16–350MHz); higher integration (integrated LDOs, no V_EE); 0.7ps jitter @125MHz.	Requires firmware initialization and I2C bus access; better suited for designs needing dynamic frequency changes or multi-rate support.	Choose Si5338A-A-GM if programmability, multi-frequency support, or simplified power design outweighs fixed-function simplicity and lower jitter of 843004AG-125LF.
ICS843004AG-125T	Same silicon die and electrical specs; differs only in tape-and-reel packaging (vs. tube for 843004AG-125LF) and marking (ICS43004A125L vs. same).	No functional or application difference - identical thermal, electrical, and timing behavior; selected solely for automated assembly compatibility.	Choose ICS843004AG-125T for SMT production lines requiring tape-and-reel feeders; otherwise 843004AG-125LF is functionally identical and suitable for prototyping or small-batch builds.

Compared with Si5338A-A-GM, the 843004AG-125LF offers lower phase jitter and zero-config operation but lacks frequency flexibility; compared with ICS843004AG-125T, it shares identical performance and pinout but differs only in packaging format - making it ideal for manual assembly or evaluation where tube delivery is preferred.

Availability

843004AG-125LF is available at Aetrix Electronics and suitable for 10GbE line cards, multi-port switch ASIC clocking, and industrial Ethernet gateways requiring stable component supply with guaranteed long-term sourcing.

Supply support for 843004AG-125LF includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Renesas Electronics Corporation is a global semiconductor leader formed through the merger of Renesas Technology and NEC Electronics, specializing in microcontrollers, analog, power, and timing solutions.

The 843004AG-125LF belongs to Renesas' FemtoClock® family of ultra-low-jitter clock synthesizers, designed specifically for high-speed networking and datacom applications demanding sub-1ps phase noise performance.

FAQ

What is the primary clock output frequency supported by the 843004AG-125LF?

The 843004AG-125LF is configured to generate a fixed 125MHz LVPECL output frequency, optimized for IEEE 802.3ae 10 Gigabit Ethernet reference clock applications. This frequency is achieved using a 25MHz crystal input with a fixed M=25 divider and internal VCO operating in the 560–680MHz range. The device does not support user-programmable output frequencies - its functionality is dedicated to this single, high-stability 125MHz output across all four differential pairs.

How does the 843004AG-125LF achieve its 0.58ps typical RMS phase jitter specification?

The 843004AG-125LF achieves 0.58ps typical RMS phase jitter (1.875MHz–20MHz offset) through IDT's third-generation low-phase-noise VCO architecture, combined with optimized charge pump design and separate analog (V_CCA) and output (V_CCO) supply domains. It is characterized using a 25MHz, 18pF parallel-resonant crystal with ESR ≤50Ω, and requires proper PCB layout - including 0.01µF bypass capacitors on all V_CC/V_CCO pins and a 10Ω + 10µF RC filter on V_CCA - to meet this jitter performance.

Can the 843004AG-125LF accept a single-ended clock input instead of a crystal?

Yes, the 843004AG-125LF supports single-ended LVCMOS/LVTTL reference clock input via the REF_CLK pin (Pin 16). When nXTAL_SEL is driven HIGH, the device routes REF_CLK directly to the PLL reference path, bypassing the crystal oscillator circuitry. The input accepts 25MHz signals with edge rates as slow as 10ns, and internal 51kΩ pulldown resistors eliminate need for external biasing - enabling flexible clock source selection without hardware modification.

What are the LVPECL termination requirements for the 843004AG-125LF outputs?

Each LVPECL output pair (e.g., Q0/nQ0) on the 843004AG-125LF must be terminated to V_CCO−2V using 50Ω transmission lines. Recommended configurations include either two 84Ω resistors (one from Q0 to V_CCO−2V, one from nQ0 to V_CCO−2V) or a Thevenin network with 125Ω resistors to V_CCO and a 84Ω resistor to ground. Improper termination causes signal reflection, degraded edge rates (>300–600ps), and increased jitter - violating the 0.58ps specification.

Is the 843004AG-125LF pin-compatible with other members of the ICS843004 family?

Yes, the 843004AG-125LF is pin-compatible with all variants in the ICS843004 family sharing the 24-pin TSSOP (G) package, including ICS843004AG-125T and legacy ICS843004-125. All share identical pin assignment, electrical characteristics, and functional block diagram - differing only in packaging format (tube vs. tape-and-reel), marking, and RoHS compliance level. No PCB redesign is required when substituting within this family.

843004AG-125LF Specifications

Product attributes: Attribute value

Manufacturer:: Renesas

Series:: FemtoClock®

Package/Case:: 24-TSSOP (0.173", 4.40mm Width)

Packaging:: Bulk

Product Status:: Obsolete

Programmable:: Not Verified

Type:: Frequency Synthesizer

PLL:: Yes with Bypass

Input:: LVCMOS, LVTTL, Crystal

Output:: LVPECL

Number of Circuits:: 1

Ratio - Input:Output:: 2:4

Differential - Input:Output:: No/Yes

Frequency - Max:: 136MHz

Divider/Multiplier:: Yes/No

Voltage - Supply:: 3.135V ~ 3.465V

Operating Temperature:: 0°C ~ 70°C

Mounting Type:: Surface Mount

Grade:: -

Qualification:: -

Supplier Device Package:: 24-TSSOP

843004AG-125LF FAQ

1.How can I place an order for 843004AG-125LF through Aetrix?

Please submit a Request for Quotation (RFQ) for 843004AG-125LF on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for 843004AG-125LF reliable?

The price and inventory of 843004AG-125LF are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 843004AG-125LF is usually 5 days.

3.What payment methods are accepted for 843004AG-125LF?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 843004AG-125LF transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for 843004AG-125LF?

843004AG-125LF orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your 843004AG-125LF order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for 843004AG-125LF?

For technical support, including 843004AG-125LF datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 843004AG-125LF requirements.

6.How does Aetrix verify that 843004AG-125LF is sourced from the original manufacturer or authorized distributors?

All 843004AG-125LF products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 843004AG-125LF meets industry standards.

7.What is the process for return or replacement of 843004AG-125LF?

All 843004AG-125LF units undergo pre-shipment inspection (PSI). If there is an issue with 843004AG-125LF, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The 843004AG-125LF part is unused and in its original packaging.

Return procedure for 843004AG-125LF:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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