Renesas 89H24NT6AG2ZAHLGI8

Overview

89H24NT6AG2ZAHLGI8 from IDT is a 24-lane, 6-port PCI Express Gen2 system interconnect switch with non-transparent bridging (NTB) and switch partitioning capabilities. It delivers up to 24 GBps switching capacity, supports 5.0 GT/s per lane, implements SECDED ECC on internal RAMs, and operates across 100/125 MHz reference clocks. It targets multi-host server and intelligent I/O subsystems requiring inter-domain PCIe communication.

For engineers reviewing the 89H24NT6AG2ZAHLGI8 datasheet, 89H24NT6AG2ZAHLGI8 pinout, 89H24NT6AG2ZAHLGI8 application, or 89H24NT6AG2ZAHLGI8 equivalent, key selection criteria include NTB endpoint count (6), partition support (up to 6 independent switches), SerDes lane configuration flexibility (x4/x2/x1 auto-negotiation), and integrated DMA controllers enabling memory-to-memory transfers across partitions.

Technical Context

The 89H24NT6AG2ZAHLGI8 implements a Combined Input Output Queued (CIOQ) switch core with large buffers and low-latency cut-through forwarding. Its architecture supports one virtual channel and eight traffic classes, with round-robin port arbitration and IDT's proprietary request metering for bandwidth balancing.

It integrates two SMBus interfaces (master and slave), dual DMA controllers (2 upstream ports × 2 channels each), and six non-transparent bridge endpoints-each with 6 BARs, 32 doorbell registers, and 4 message registers. All PCIe lanes comply with PCI Express Base Specification 2.1, including AER, ECRC, ACS, and multicast support.

Key Specifications

Pinout & Package

Packaged in a 23 mm × 23 mm 484-ball Flip Chip BGA (FCBGA) with 1 mm ball pitch. Pin functions are defined per lane and port group, with dedicated differential SerDes I/O, reference clock inputs, SMBus interfaces, GPIOs, and JTAG test signals.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe Gen2 switching applications.

Compared with 89H24NT6AG2ZAHLGI8, the 89H24NT6AG2ZCBLGI offers identical performance in a commercial temperature grade, while the 89H12NT6AG2ZAHLGI reduces lane count and power but retains full NTB and partitioning features-enabling scalable design reuse across performance tiers.

Availability

89H24NT6AG2ZAHLGI8 is available at Aetrix Electronics and suitable for multi-host servers, intelligent I/O expansion systems, and telecom backplane designs requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for 89H24NT6AG2ZAHLGI8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

IDT (Integrated Device Technology, Inc.) is a fabless semiconductor company specializing in timing, interface, and interconnect solutions for high-performance computing and communications infrastructure.

The 89H24NT6AG2ZAHLGI8 belongs to IDT's PES (PCI Express Switch) family, designed specifically to enable scalable, reliable, and feature-rich PCIe Gen2 interconnects in multi-root and domain-isolated systems.

FAQ

What is the maximum number of non-transparent bridge endpoints supported by the 89H24NT6AG2ZAHLGI8?

The 89H24NT6AG2ZAHLGI8 supports up to 6 non-transparent bridge (NTB) endpoints. Each endpoint provides 6 BARs, 32 doorbell registers, and 4 message registers to enable memory-mapped communication across PCIe domains. This capability is confirmed in the device overview and Table 1 of the official datasheet, and it is integral to the chip's role in multi-host server and intelligent I/O applications.

Does the 89H24NT6AG2ZAHLGI8 support PCIe Gen3 speeds?

No, the 89H24NT6AG2ZAHLGI8 supports only PCIe Gen1 (2.5 GT/s) and Gen2 (5.0 GT/s) operation. The datasheet explicitly states "Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s Gen1 operation" and confirms compliance with PCI Express Base Specification 2.1-not 3.0 or later. No Gen3 capability is implemented in this device.

How many independent switch partitions can be configured on the 89H24NT6AG2ZAHLGI8?

The 89H24NT6AG2ZAHLGI8 supports up to 6 fully independent switch partitions. These partitions operate as logically isolated switches within the same physical device, with configurable downstream port numbering and dynamic reconfiguration-including port migration and upstream port movement. This is a core feature documented in the "Innovative Switch Partitioning Feature" section of the datasheet.

What reference clock frequencies does the 89H24NT6AG2ZAHLGI8 accept?

The 89H24NT6AG2ZAHLGI8 accepts 100 MHz or 125 MHz differential reference clock inputs, selected via the GCLKFSEL pin. Both global clock pairs (GCLKN/GCLKP) must derive from the same source. This is specified in the "Clocking" feature list and verified in Table 11 ("Input Clock Requirements") of the datasheet.

Is the 89H24NT6AG2ZAHLGI8 pin-compatible with other members of the PES24NT6AG2 family?

Yes, the 89H24NT6AG2ZAHLGI8 shares the same 484-ball FCBGA package and pinout with other variants in the PES24NT6AG2 family, including 89H24NT6AG2ZCBLGI and 89H24NT6AG2ZAHLGI. All share identical ball mapping, power sequencing, and signal definitions-as confirmed in the "Pin Description" and "Pin Characteristics" sections of the datasheet.