Renesas 89H24NT6AG2ZAHLI8
- Part No.:
- 89H24NT6AG2ZAHLI8
- Manufacturer:
- Renesas
- Category:
- Specialized
- Package:
- 484-BBGA, FCBGA
- Datasheet:
-
89H24NT6AG2ZAHLI8.pdf
- Description:
- IC INTFACE SPECIALIZED 484FCBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
89H24NT6AG2ZAHLI8 from IDT is a 24-lane, 6-port PCI Express Gen2 system interconnect switch with Non-Transparent Bridging (NTB) and Switch Partitioning capabilities. It delivers up to 24 GBps switching capacity, supports 5.0 GT/s link speed per lane, and operates in servers, storage systems, and intelligent I/O subsystems requiring multi-domain peer-to-peer communication.
For engineers reviewing the 89H24NT6AG2ZAHLI8 datasheet, 89H24NT6AG2ZAHLI8 pinout, 89H24NT6AG2ZAHLI8 application, or 89H24NT6AG2ZAHLI8 equivalent, key selection criteria include NTB endpoint count (up to 6), partitioned switch configuration flexibility, PCIe Base Specification 2.1 compliance, and support for dynamic port reconfiguration across partitions.
Technical Context
The 89H24NT6AG2ZAHLI8 implements a Combined Input Output Queued (CIOQ) switch core with large buffers and low-latency cut-through forwarding. Its integrated SerDes supports both Gen1 (2.5 GT/s) and Gen2 (5.0 GT/s) operation, with per-lane configuration for de-emphasis, receive equalization, and drive strength.
It features dual SMBus interfaces (master and slave), on-die temperature sensing (0–127.5°C), and IEEE 1149.1/1149.6 JTAG support. The device enables up to 6 independent switch partitions, each configurable with downstream port numbering and movable upstream ports - enabling true multi-host domain isolation without external logic.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Lanes / Ports | 24 PCIe lanes across 6 x4 ports - enables flexible topology mapping including crosslink and automatic lane reversal. |
| PCIe Generation | Gen2 compliant (5.0 GT/s) with backward Gen1 (2.5 GT/s) support - ensures interoperability with legacy endpoints. |
| Switching Capacity | 24 GBps (192 Gbps) non-blocking throughput - sustains full bandwidth across all ports simultaneously. |
| NTB Endpoints | Up to 6 NTB endpoints, each with 6 BARs and 32 doorbell registers - enables scalable inter-domain memory-mapped communication. |
| Partitioning | Up to 6 fully independent logical switches in one die - allows dynamic port migration and reconfiguration without reset. |
| Power Supplies | Three rails: 1.0V (core), 2.5V (SerDes analog high), 3.3V (I/O) - requires discrete regulation per rail for signal integrity. |
| Reference Clock | 100 MHz or 125 MHz differential input (GCLKFSEL-selectable) - supports common clock, non-common clock, and local port clock modes. |
| Package | 484-ball Flip Chip BGA, 23 mm × 23 mm, 1.0 mm ball pitch - compatible with standard PCB assembly processes. |
Pinout & Package
Package: 484-ball Flip Chip BGA (23 mm × 23 mm, 1.0 mm pitch). Ball map includes six PCIe x4 ports (Port 0, 2, 4, 6, 8, 12), dual differential reference clocks (global and per-port), dual SMBus interfaces, 9 GPIOs with alternate functions (e.g., PARTxPERSTN, P0LINKUPN), JTAG test pins, and dedicated power/ground balls for VDDCORE, VDDI/O, VDDPEA, VDDPEHA, VDDPETA, and VSS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| PE00RN[3:0]/RP[3:0] | PCIe Port 0 Receive Differential Pair | Lane-level Rx inputs for Port 0 - AC-coupled, require external 100Ω differential termination. |
| PE00TN[3:0]/TP[3:0] | PCIe Port 0 Transmit Differential Pair | Lane-level Tx outputs for Port 0 - support programmable de-emphasis and drive strength. |
| GCLKN[1:0]/GCLKP[1:0] | Global Reference Clock Input | Differential 100/125 MHz clock source for internal PLLs - both pairs must derive from same oscillator. |
| MSMBCLK/MSMBDAT | SMBus Master Interface | Controls external serial EEPROM and hot-plug I/O expander - requires pull-up resistors per SMBus spec. |
| SSMBCLK/SSMBDAT | SMBus Slave Interface | Allows external host CPU or BMC to configure registers in real time - supports full register read/write access. |
| GPIO[0]–GPIO[8] | Configurable General Purpose I/O | Each supports primary I/O mode or alternate functions like partition reset (PARTxPERSTN) or link status (P0LINKUPN). |
| JTAG_TCK/TDI/TDO/TMS/TRST_N | IEEE 1149.1/1149.6 Boundary Scan | Enables production testing, debug, and AER error injection - TRST_N requires active-low assertion. |
Key Features
| Feature | Design Value |
|---|---|
| Non-Transparent Bridging (NTB) | 6 independent NTB endpoints with BAR address translation, 32 doorbell registers, and 4 message registers - enables secure, memory-isolated communication between PCIe domains. |
| Switch Partitioning | Up to 6 logically isolated switch partitions with dynamic port reassignment - eliminates need for multiple physical switches in multi-host systems. |
| Integrated DMA Controllers | 2 upstream DMA ports, each with 2 channels supporting 32/64-bit memory-to-memory transfers - offloads CPU for inter-partition and multicast data movement. |
| Hot-Plug Support | Per-port hot-plug controller with GPE output and I²C I/O expander interface - enables legacy OS-compatible card insertion/removal without system reboot. |
| RAS Enhancements | SECDED ECC on all internal RAMs, end-to-end parity, ECRC regeneration, and AER on all ports - meets enterprise-grade reliability requirements. |
| Flexible Clocking | Support for common clock, non-common clock, and local port clock with SSC - simplifies board-level clock tree design across heterogeneous topologies. |
Applications
| Enterprise Storage Arrays | Multi-Host Server Backplanes |
|---|---|
|
Use Scenario: High-availability storage controllers requiring redundant host access to shared NVMe JBOD enclosures via separate PCIe root complexes. IC Role / Device Role / Timing Role: Acts as a partitioned PCIe switch with NTB endpoints bridging two independent CPU domains to shared storage resources. Use Value: Enables simultaneous, isolated access to identical LUNs by dual hosts while maintaining cache coherency through BAR-based address translation and doorbell signaling. |
Use Scenario: Rack-scale server architectures where CPU modules must communicate peer-to-peer over PCIe without traversing the motherboard chipset. IC Role / Device Role / Timing Role: Functions as a multi-partition interconnect switch, allocating dedicated lanes and routing tables per CPU module. Use Value: Eliminates bottlenecks from centralized I/O hubs by enabling direct CPU-to-CPU traffic flow with sub-100ns latency cut-through forwarding. |
| Intelligent I/O Accelerators | Communications Equipment |
|
Use Scenario: FPGA-based SmartNICs performing packet processing and offloading, requiring direct memory access to host DRAM across PCIe boundaries. IC Role / Device Role / Timing Role: Serves as an NTB-enabled bridge between the FPGA's PCIe endpoint and host CPU memory space. Use Value: Supports 64-bit BAR windows and fly-by DMA transfers - enabling zero-copy, high-throughput data movement without CPU intervention. |
Use Scenario: Carrier-grade routers with modular line cards that hot-swap while maintaining control plane continuity across multiple management CPUs. IC Role / Device Role / Timing Role: Provides hot-plug-aware PCIe switching with GPE-driven SCI/SMI generation for legacy BIOS compatibility. Use Value: Ensures uninterrupted service during field upgrades by isolating failed line cards and dynamically reassigning upstream ports within surviving partitions. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe Gen2 switching applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 89H24NT6AG2ZCBLI8 | Same silicon, different temperature grade (–40°C to +85°C vs. –40°C to +105°C) and ball finish (SnAgCu vs. Pb-free matte Sn). | Targeted at commercial/industrial environments with less extreme thermal cycling; lacks extended junction temperature rating. | Select when operating ambient stays below 85°C and RoHS-compliant matte Sn finish is acceptable. |
| 89H32NT6AG2ZCBLI8 | 32-lane variant with identical feature set, NTB, and partitioning - adds two extra x4 ports (Ports 10 and 14) and increases switching capacity to 32 GBps. | Required for topologies needing >24 lanes (e.g., 8× GPU servers or multi-DPU AI accelerators); larger package (27 mm × 27 mm). | Choose when scaling beyond 24 lanes is needed and board area allows larger BGA footprint. |
Compared with 89H24NT6AG2ZAHLI8, the ZCBLI8 variant trades junction temperature margin for cost and thermal simplicity, while the 32-lane alternative extends scalability at the expense of PCB real estate and power - making the 89H24NT6AG2ZAHLI8 optimal for balanced performance, density, and extended-temperature robustness in mission-critical infrastructure.
Availability
89H24NT6AG2ZAHLI8 is available at Aetrix Electronics and suitable for enterprise storage arrays, multi-host server backplanes, intelligent I/O accelerators, and carrier-grade communications equipment requiring stable component supply across long product lifecycles.
Supply support for 89H24NT6AG2ZAHLI8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
IDT (Integrated Device Technology) is a fabless semiconductor company specializing in timing, memory interface, RF, and high-performance interconnect solutions, acquired by Renesas Electronics in 2019.
The 89H24NT6AG2ZAHLI8 belongs to IDT's PCIe Express Switch family, designed specifically for high-reliability, multi-domain system interconnect in datacenter and telecom infrastructure where NTB and partitioning are essential.
FAQ
What is the maximum PCIe link speed supported by the 89H24NT6AG2ZAHLI8?
The 89H24NT6AG2ZAHLI8 supports PCIe Gen2 with a maximum link speed of 5.0 GT/s per lane. It is fully compliant with the PCI Express Base Specification 2.1 and maintains backward compatibility with Gen1 (2.5 GT/s) links. Each of its 24 lanes operates independently at either speed, depending on negotiation with connected endpoints.
Does the 89H24NT6AG2ZAHLI8 support Non-Transparent Bridging (NTB)?
Yes, the 89H24NT6AG2ZAHLI8 natively supports NTB with up to 6 independent NTB endpoints. Each endpoint provides 6 BARs for address translation, 32 doorbell registers for event signaling, and 4 message registers for mailbox-style communication - enabling secure, memory-isolated data exchange between separate PCIe domains.
How many independent switch partitions can be configured on the 89H24NT6AG2ZAHLI8?
The 89H24NT6AG2ZAHLI8 supports up to 6 fully independent switch partitions. These partitions operate as logically isolated switches sharing the same silicon, with configurable downstream port numbering and dynamic port migration - allowing runtime reconfiguration without device reset.
What reference clock frequencies does the 89H24NT6AG2ZAHLI8 accept?
The 89H24NT6AG2ZAHLI8 accepts 100 MHz or 125 MHz differential reference clock inputs, selected via the GCLKFSEL pin. It supports multiple clocking modes including common clock, non-common clock, and local port clock with spread-spectrum capability - accommodating diverse board-level clock distribution schemes.
Is the 89H24NT6AG2ZAHLI8 pin-compatible with other members of the PES24NT6AG2 family?
Yes, the 89H24NT6AG2ZAHLI8 shares identical pinout and package (484-ball FC-BGA, 23 mm × 23 mm) with all variants in the PES24NT6AG2 family, including ZCBLI8 and ZABLIG8. Differences are limited to temperature grade, ball finish, and marking - enabling drop-in replacement where thermal and reliability requirements align.
What power supply voltages are required for the 89H24NT6AG2ZAHLI8?
The 89H24NT6AG2ZAHLI8 requires three distinct power supplies: 1.0V for core logic (VDDCORE), 2.5V for high-power SerDes analog circuitry (VDDPEHA), and 3.3V for I/O buffers (VDDI/O). Additional 1.0V rails (VDDPEA, VDDPETA) power SerDes analog and transmitter sections - all must meet tight tolerance and sequencing requirements per datasheet.
89H24NT6AG2ZAHLI8 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Renesas
- Series:
- -
- Package/Case:
- 484-BBGA, FCBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Applications:
- Switch Interfacing
- Interface:
- PCI Express
- Voltage - Supply:
- 3.3V
- Supplier Device Package:
- 484-FCBGA (23x23)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
89H24NT6AG2ZAHLI8 FAQ
1.How can I place an order for 89H24NT6AG2ZAHLI8 through Aetrix?
Please submit a Request for Quotation (RFQ) for 89H24NT6AG2ZAHLI8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 89H24NT6AG2ZAHLI8 reliable?
The price and inventory of 89H24NT6AG2ZAHLI8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 89H24NT6AG2ZAHLI8 is usually 5 days.
3.What payment methods are accepted for 89H24NT6AG2ZAHLI8?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 89H24NT6AG2ZAHLI8 transactions.
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89H24NT6AG2ZAHLI8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 89H24NT6AG2ZAHLI8 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 89H24NT6AG2ZAHLI8?
For technical support, including 89H24NT6AG2ZAHLI8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 89H24NT6AG2ZAHLI8 requirements.
6.How does Aetrix verify that 89H24NT6AG2ZAHLI8 is sourced from the original manufacturer or authorized distributors?
All 89H24NT6AG2ZAHLI8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 89H24NT6AG2ZAHLI8 meets industry standards.
7.What is the process for return or replacement of 89H24NT6AG2ZAHLI8?
All 89H24NT6AG2ZAHLI8 units undergo pre-shipment inspection (PSI). If there is an issue with 89H24NT6AG2ZAHLI8, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 89H24NT6AG2ZAHLI8 part is unused and in its original packaging.
Return procedure for 89H24NT6AG2ZAHLI8:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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