Microchip Technology 93AA46AT-I/MNY
- Part No.:
- 93AA46AT-I/MNY
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-WFDFN Exposed Pad
- Datasheet:
-
93AA46AT-I/MNY.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8TDFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,601
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
93AA46AT-I/MNY from Microchip Technology Inc. is a 1 Kbit (128 × 8-bit) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, 1.8–5.5 V supply range, and industrial temperature rating (–40°C to +85°C). It features self-timed erase/write cycles, automatic erase-all-before-write-all (ERAL/WRAL), power-on/off data protection, and Ready/Busy status signaling via DO pin - deployed in embedded system configuration storage, sensor calibration memory, and firmware parameter retention.
For engineers reviewing the 93AA46AT-I/MNY datasheet, 93AA46AT-I/MNY pinout, 93AA46AT-I/MNY application, or 93AA46AT-I/MNY equivalent, key selection considerations include its fixed 8-bit organization (no ORG pin), 8-lead MSOP package, 1 million erase/write endurance, 200+ year data retention, and compatibility with low-power microcontroller peripherals requiring serial nonvolatile memory with hardware write protection.
Technical Context
The 93AA46AT-I/MNY implements a synchronous Microwire protocol using CS, CLK, and DI/DO lines - no ORG pin required due to fixed x8 architecture. Its internal logic enforces power-on write disable (EWDS), requiring explicit EWEN before any erase or write operation, and supports sequential read with automatic address increment while CS remains high.
Timing is governed by voltage-dependent clock frequency limits (up to 3 MHz at VCC ≥ 4.5 V), with guaranteed TPD ≤ 400 ns and TWC = 6 ms for erase/write cycles. The device asserts Ready/Busy on DO after CS reactivation post-command, enabling polling-based host synchronization without external wait states.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Kbit (128 words × 8 bits) - provides compact, byte-addressable nonvolatile storage for small configuration sets. |
| Interface | Microwire-compatible 3-wire serial (CS/CLK/DI/DO) - requires only four MCU GPIOs and no address bus or parallel data lines. |
| VCC Range | 1.8 V to 5.5 V - supports direct interfacing with 1.8 V, 3.3 V, and 5 V logic domains without level shifters. |
| Endurance | 1,000,000 erase/write cycles - enables frequent runtime updates in logging, calibration, or adaptive control applications. |
| Data Retention | Greater than 200 years at +25°C - ensures long-term reliability in unattended or maintenance-free deployments. |
| Operating Temp | –40°C to +85°C (Industrial grade) - qualified for use in automotive ECUs, industrial controllers, and outdoor IoT nodes. |
| Write Cycle Time | 6 ms typical (TWC) - defines minimum interval between successive write commands; enables deterministic firmware update timing. |
Pinout & Package
93AA46AT-I/MNY is packaged in an 8-lead MSOP (Micro Small Outline Package) with 0.65 mm lead pitch and exposed pad (optional VSS connection). Pin 1 is marked by laser indentation; package conforms to JEDEC MO-187AA.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select | Active-high enable signal; must be held low ≥250 ns between instructions to reset internal state and prevent spurious command latching. |
| 2 (CLK) | Serial Clock | Synchronizes all data transfers; rising edge clocks opcode/address/data into DI and clocks data out of DO. |
| 3 (DI) | Data Input | Receives Start bit, instruction opcodes, addresses, and write data; tied high during Start condition detection. |
| 4 (DO) | Data Output / Status | Outputs read data or Ready/Busy status (low = busy); enters High-Z when CS is low or during non-read operations. |
| 5 (VSS) | Ground | Reference return path for all I/O and core logic; exposed pad may be connected to PCB ground plane for thermal and EMI performance. |
| 6 (NC) | No Connect | Internally unconnected; must be left floating or tied to VSS per layout best practice - no functional role. |
| 7 (NC) | No Connect | Second NC terminal; identical handling as Pin 6 - no routing or loading required. |
| 8 (VCC) | Power Supply | Core and I/O supply; includes internal POR circuit triggering at ~1.5 V - prevents corruption during brown-out conditions. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Erase/Write | Eliminates need for external timing control or software delays - host initiates command and polls DO for completion. |
| Automatic ERAL before WRAL | Ensures full array is erased prior to bulk write, preventing partial-data corruption without requiring separate erase sequence. |
| Power-On/Off Data Protection | Hardware-enforced write inhibit below VCC threshold (~1.5 V) - guarantees memory integrity during power ramp-up/down. |
| Ready/Busy Status on DO | Enables efficient polling-based host synchronization without dedicated interrupt lines or fixed timeout loops. |
| Low Standby Current | ≤1 µA (ICCS) at I-temp - extends battery life in always-on sensor nodes and portable instrumentation. |
Applications
| Industrial PLC Configuration Storage | Medical Device Calibration Memory |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and user-defined alarm thresholds in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed during boot and runtime via SPI-compatible Microwire interface. Use Value: Enables field-upgradable settings without firmware reflashing; 200-year retention ensures parameter persistence across equipment lifetime. |
Use Scenario: Holding factory-calibrated sensor offsets and gain coefficients in portable blood glucose meters and infusion pumps. IC Role / Device Role / Timing Role: Secure, tamper-resistant parameter store accessed during device initialization and self-test sequences. Use Value: Meets IEC 62304 Class B requirements for data integrity; 1M-cycle endurance supports recalibration during service intervals. |
| Automotive Body Control Module (BCM) | Smart Energy Meter Firmware Parameters |
Use Scenario: Retaining seat/mirror position presets, lighting profiles, and door lock configurations in 12 V automotive BCMs. IC Role / Device Role / Timing Role: Low-voltage EEPROM interfaced directly to 3.3 V microcontroller with integrated Microwire peripheral. Use Value: 1.8–5.5 V operation tolerates battery transients; industrial temp rating covers under-hood ambient extremes. |
Use Scenario: Storing tariff schedules, demand-response thresholds, and metering calibration constants in ANSI C12.20-compliant smart meters. IC Role / Device Role / Timing Role: Tamper-evident configuration memory updated infrequently but requiring absolute data integrity over 15+ year deployment. Use Value: RoHS-compliant Pb-free finish and 200-year retention satisfy utility-grade longevity and environmental compliance mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC46AT-I/MNY | Same 128×8 organization and MSOP-8 package, but wider VCC range starts at 2.5 V (vs. 1.8 V). | Not suitable for 1.8 V systems; otherwise functionally identical in timing, instruction set, and endurance. | Select 93AA46AT-I/MNY for true 1.8 V operation; choose 93LC46AT-I/MNY if system VCC never drops below 2.5 V and legacy design reuse is prioritized. |
| AT25010B-MAHL-T | 1 Kbit SPI EEPROM (not Microwire), 2.5–5.5 V, SOIC-8, 5 MHz max clock, no ERAL/WRAL auto-erase. | Lacks automatic erase-all-before-write-all; requires explicit erase commands and supports standard SPI mode 0/3 only. | Use AT25010B-MAHL-T only when migrating to SPI infrastructure; 93AA46AT-I/MNY remains optimal for Microwire-native designs with auto-erase requirements. |
Compared with 93LC46AT-I/MNY and AT25010B-MAHL-T, the 93AA46AT-I/MNY uniquely delivers 1.8 V compatibility and integrated ERAL/WRAL auto-erase functionality in the same MSOP-8 footprint - critical for ultra-low-power and safety-critical configuration storage where voltage margin and data consistency are non-negotiable.
Availability
93AA46AT-I/MNY is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, automotive body electronics, and smart metering applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for 93AA46AT-I/MNY includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design, manufacturing, and sales operations.
The 93AA46A/B/C series was designed specifically for cost-sensitive, low-power embedded systems needing reliable serial EEPROM with hardware-level data protection and flexible voltage operation - targeting industrial control, consumer electronics, and automotive subsystems.
FAQ
What is the memory organization of the 93AA46AT-I/MNY?
The 93AA46AT-I/MNY has a fixed 128 × 8-bit (1 Kbit) organization with no ORG pin - unlike 'C' variants, it does not support word-size selection. This simplifies hardware design by eliminating external ORG pull-up/pull-down requirements and guarantees consistent 8-bit data framing for all read/write operations.
Does the 93AA46AT-I/MNY require an external pull-up resistor on the DO line?
No, the 93AA46AT-I/MNY drives DO actively during read and Ready/Busy status reporting; however, a 10 kΩ pull-down on CS is recommended per Microchip's application guidance to prevent spurious activation during power-up. DO operates in true three-state (High-Z) when inactive, so no pull-up is needed unless shared-bus contention is present.
How does the 93AA46AT-I/MNY handle power loss during a write cycle?
The 93AA46AT-I/MNY incorporates power-on/off data protection that inhibits all write operations when VCC falls below ~1.5 V. If power loss occurs mid-cycle, the internal charge pump cannot complete programming, and the affected memory location remains unaltered - ensuring atomicity and preventing partial writes or corruption.
Can the 93AA46AT-I/MNY be used with a 5 V microcontroller?
Yes, the 93AA46AT-I/MNY supports VCC from 1.8 V to 5.5 V and is fully compatible with 5 V logic levels: VIH1 = 2.0 V min (for VCC ≥ 2.7 V), and VOH1 = 2.4 V min at IOH = –400 µA - meeting standard TTL/CMOS input thresholds and ensuring robust interoperability without level translation.
What is the purpose of the NC pins on the 93AA46AT-I/MNY MSOP package?
Pins 6 and 7 of the 93AA46AT-I/MNY MSOP package are No Connect (NC) terminals - internally unconnected and electrically inert. They must be left floating or tied to VSS per PCB layout guidelines; routing signals or applying voltage to these pins has no functional effect and risks violating package mechanical integrity.
93AA46AT-I/MNY Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 6ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-TDFN (2x3)
93AA46AT-I/MNY FAQ
1.How can I place an order for 93AA46AT-I/MNY through Aetrix?
Please submit a Request for Quotation (RFQ) for 93AA46AT-I/MNY on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93AA46AT-I/MNY reliable?
The price and inventory of 93AA46AT-I/MNY are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93AA46AT-I/MNY is usually 5 days.
3.What payment methods are accepted for 93AA46AT-I/MNY?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93AA46AT-I/MNY transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93AA46AT-I/MNY?
93AA46AT-I/MNY orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93AA46AT-I/MNY order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93AA46AT-I/MNY?
For technical support, including 93AA46AT-I/MNY datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93AA46AT-I/MNY requirements.
6.How does Aetrix verify that 93AA46AT-I/MNY is sourced from the original manufacturer or authorized distributors?
All 93AA46AT-I/MNY products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93AA46AT-I/MNY meets industry standards.
7.What is the process for return or replacement of 93AA46AT-I/MNY?
All 93AA46AT-I/MNY units undergo pre-shipment inspection (PSI). If there is an issue with 93AA46AT-I/MNY, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93AA46AT-I/MNY part is unused and in its original packaging.
Return procedure for 93AA46AT-I/MNY:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
93AA46AT-I/MNY Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

