Microchip Technology 93AA46AXT-I/SN
- Part No.:
- 93AA46AXT-I/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
93AA46AXT-I/SN.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
93AA46AXT-I/SN from Microchip Technology is a 1 Kbit (128 × 8-bit) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, 1.8–5.5 V supply range, and industrial temperature rating (–40°C to +85°C). It features self-timed erase/write cycles, automatic erase-all-before-write-all (ERAL/WRAL), power-on/off data protection, and Ready/Busy status signaling via DO pin - used in microcontroller firmware storage, calibration data retention, and configuration memory for embedded sensors.
For engineers reviewing the 93AA46AXT-I/SN datasheet, 93AA46AXT-I/SN pinout, 93AA46AXT-I/SN application, or 93AA46AXT-I/SN equivalent, key selection criteria include its dedicated 8-bit organization (no ORG pin), SOIC-8 package compatibility, 1 million erase/write endurance, >200-year data retention, and support for sequential read and status polling during programming.
Technical Context
This device implements a synchronous serial Microwire protocol with CS, CLK, and DI/DO pins. It uses internal auto-erase before write, eliminating external erase commands for single-byte operations. The absence of an ORG pin confirms fixed 8-bit word width, simplifying host controller timing and eliminating configuration logic.
Power-on reset circuitry holds the device in Erase/Write Disable (EWDS) mode until an explicit EWEN command is issued. All programming operations require this enable step, and the DO pin serves dual function: data output during READ and Ready/Busy status indicator during ERASE/WRITE - verified by sampling after minimum TCSL (250 ns).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 1 Kbit (128 × 8-bit); fixed x8 organization - no ORG pin required, simplifies PCB layout and firmware driver design. |
| VCC range | 1.8 V to 5.5 V; supports direct interfacing with 1.8 V, 3.3 V, and 5 V microcontrollers without level shifters. |
| Endurance | 1,000,000 erase/write cycles; enables reliable field-updatable parameter storage in industrial control systems. |
| Data retention | >200 years at +25°C; ensures long-term calibration data integrity in unpowered equipment. |
| Max clock frequency | 3 MHz at VCC ≥ 4.5 V; allows fast configuration loading while maintaining compatibility with legacy Microwire hosts. |
| Write cycle time | 6 ms typical (TWC); deterministic self-timed programming eliminates need for host wait-state management. |
| Standby current | 1 µA (I-temp); critical for battery-powered IoT nodes where EEPROM must remain powered but inactive for months. |
Pinout & Package
93AA46AXT-I/SN is supplied in an 8-lead SOIC package (SN suffix), with standard pinout and Pb-free Matte Tin finish. Pin 1 is marked by laser dot; exposed pad not present in SOIC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-high enable; device enters Standby mode when low, but completes ongoing write before sleeping - prevents data corruption on power-down. |
| CLK | Serial Clock | Positive-edge synchronized I/O; supports clock stretching and pause between bits - accommodates slow or resource-constrained MCUs. |
| DI | Data Input | Accepts Start bit, opcodes (e.g., 01 for WRITE), addresses (7-bit), and data (8-bit); no pull-up required if driven actively. |
| DO | Data Output / Status | Tri-state output; delivers read data or indicates Ready (high) / Busy (low) during programming - enables non-blocking polling. |
| VSS | Ground | Reference for all I/O and internal logic; must be low-impedance connection to avoid timing violations. |
| NC | No Connection | Pin 7 is internally unconnected; must be left floating or tied to VSS per layout best practice - no functional impact. |
| VCC | Power Supply | 1.8–5.5 V input; internal voltage detect (VPOR = 1.5 V) blocks writes below threshold - prevents partial writes during brown-out. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed erase/write | Eliminates external timing control - host only needs to issue command and poll DO; reduces firmware complexity and CPU overhead. |
| Automatic ERAL before WRAL | Ensures full array is erased prior to bulk write - guarantees consistent data state without requiring separate erase command sequence. |
| Power-on/off data protection | Hardware-level lockout below VPOR (1.5 V) prevents spurious writes during power ramp-up/down - critical for automotive and industrial environments. |
| Sequential read mode | Enables continuous address incrementing with CS held high - reduces transaction overhead for reading multi-byte configuration blocks. |
| Ready/Busy status on DO | Allows real-time progress monitoring without additional pins or status registers - simplifies interface design versus I²C or SPI EEPROMs requiring separate status polling. |
Applications
| Industrial Sensor Calibration | Microcontroller Firmware Storage |
|---|---|
Use Scenario: Storing factory-calibrated offset/gain coefficients for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory holding trim values accessed at boot; 8-bit word width matches ADC register alignment. Use Value: Eliminates need for external trimming potentiometers; enables field recalibration via UART/USB and persistent save using 1.8 V compatible interface. | Use Scenario: Holding bootloader configuration flags, secure boot keys, or peripheral initialization parameters in ARM Cortex-M0+ based edge devices. IC Role / Device Role / Timing Role: Dedicated parameter store decoupled from main flash; accessed via GPIO-banged Microwire during early boot before clock tree stabilization. Use Value: Provides tamper-resistant, low-power storage independent of MCU flash endurance limits - extends product lifetime beyond 1M reprogramming cycles. |
| Smart Meter Configuration | Medical Device Settings Backup |
Use Scenario: Retaining tariff schedules, pulse constants, and communication module settings in ANSI C12.22-compliant electricity meters. IC Role / Device Role / Timing Role: Tamper-evident configuration vault; write-protected via EWEN/EWDS protocol during normal operation. Use Value: Meets IEC 62056-21 security requirements through hardware-enforced write disable; 200-year retention exceeds 20-year meter service life. | Use Scenario: Preserving user-adjusted therapy parameters (e.g., infusion rate, alarm thresholds) across power cycles in portable insulin pumps. IC Role / Device Role / Timing Role: Fail-safe settings memory with brown-out immunity; retains data even during battery swap or low-VCC conditions. Use Value: Complies with IEC 62304 Class B software safety requirements by guaranteeing parameter persistence without software-managed wear leveling. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC46A-I/SN | Same 128×8 organization, but 2.5–5.5 V VCC range; lacks 1.8 V operation. | Not suitable for 1.8 V systems; requires minimum 2.5 V - excludes ultra-low-power sensor nodes. | Select only if system VCC ≥ 2.5 V and 1.8 V compatibility is unnecessary. |
| AT25010B-SSHL-T | SPI interface (4-wire), 1 Kbit, 1.8–5.5 V; no Ready/Busy pin - relies on WIP flag in status register. | Requires SPI master with status register polling; adds 1 pin (SCK/MOSI/MISO/CS) vs. Microwire's 3-wire simplicity. | Choose when existing design uses SPI peripherals and firmware already supports status register reads. |
Compared with 93LC46A-I/SN, 93AA46AXT-I/SN enables lower-voltage operation down to 1.8 V, extending battery life in portable devices; compared with AT25010B-SSHL-T, it offers simpler 3-wire timing and dedicated DO-status signaling, reducing MCU GPIO count and interrupt handling complexity.
Availability
93AA46AXT-I/SN is available at Aetrix Electronics and suitable for industrial sensor calibration, microcontroller firmware storage, smart meter configuration, and medical device settings backup requiring stable component supply across extended production lifecycles.
Supply support for 93AA46AXT-I/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona.
The 93XX46 family was designed specifically for cost-sensitive, low-power embedded systems requiring simple, robust, and long-life nonvolatile storage - emphasizing Microwire compatibility, wide VCC range, and hardware data protection.
FAQ
What is the memory organization of the 93AA46AXT-I/SN?
The 93AA46AXT-I/SN has a fixed 128 × 8-bit (1 Kbit) organization with no ORG pin - confirming dedicated 8-bit word width. This eliminates configuration logic and simplifies host interface timing versus ORG-pin variants like the 93AA46C. The device does not support 16-bit mode, and all instructions (READ, WRITE, ERASE) operate on 8-bit data units as defined in Table 1-4 of DS20001749K.
Does the 93AA46AXT-I/SN require an external pull-up resistor on the DO pin?
No, the 93AA46AXT-I/SN does not require an external pull-up on DO. The pin is actively driven high or low during READ or Ready/Busy status reporting, and enters High-Z only when CS is low or during EWDS mode. However, if DI and DO are shorted (shared bus), a series resistor is recommended to prevent bus conflict during the dummy zero preceding READ - as noted in Section 2.2 of the datasheet.
How does the 93AA46AXT-I/SN handle power loss during a write operation?
The 93AA46AXT-I/SN incorporates hardware power-loss protection: its internal voltage detector (VPOR = 1.5 V) disables all write functions when VCC drops below this threshold. This ensures that incomplete erase/write cycles are aborted cleanly, preventing partial or corrupted data. Combined with automatic erase-before-write and self-timed cycles, this guarantees atomic updates even during brown-out events.
Can the 93AA46AXT-I/SN be used with a 1.8 V microcontroller without level shifting?
Yes, the 93AA46AXT-I/SN operates natively from 1.8 V to 5.5 V and meets all DC and AC specifications across this range - including VIH/VIL thresholds and timing parameters. Its 1.8 V minimum VCC and guaranteed 3 MHz clock speed at 4.5–5.5 V make it fully compatible with 1.8 V MCUs such as the MSP430FRxx or EFM32 Zero Gecko, with no level-shifting circuitry required.
What is the purpose of the NC pin (Pin 7) on the 93AA46AXT-I/SN SOIC package?
Pin 7 on the 93AA46AXT-I/SN is designated NC (No Connection) and is internally unconnected. Per Microchip's Package Types diagram (DS20001749K-page 2), it must be left floating or tied to VSS for mechanical stability - it has no electrical function. This distinguishes it from the ORG pin found on 'C' variants, confirming the 93AA46AXT-I/SN's fixed 8-bit architecture.
93AA46AXT-I/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 6ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
93AA46AXT-I/SN FAQ
1.How can I place an order for 93AA46AXT-I/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 93AA46AXT-I/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93AA46AXT-I/SN reliable?
The price and inventory of 93AA46AXT-I/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93AA46AXT-I/SN is usually 5 days.
3.What payment methods are accepted for 93AA46AXT-I/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93AA46AXT-I/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93AA46AXT-I/SN?
93AA46AXT-I/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93AA46AXT-I/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93AA46AXT-I/SN?
For technical support, including 93AA46AXT-I/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93AA46AXT-I/SN requirements.
6.How does Aetrix verify that 93AA46AXT-I/SN is sourced from the original manufacturer or authorized distributors?
All 93AA46AXT-I/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93AA46AXT-I/SN meets industry standards.
7.What is the process for return or replacement of 93AA46AXT-I/SN?
All 93AA46AXT-I/SN units undergo pre-shipment inspection (PSI). If there is an issue with 93AA46AXT-I/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93AA46AXT-I/SN part is unused and in its original packaging.
Return procedure for 93AA46AXT-I/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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