Microchip Technology 93AA46XT/SN
- Part No.:
- 93AA46XT/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
93AA46XT/SN.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,931
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Product details
Overview
93AA46XT/SN from Microchip Technology Inc. is a 1K-bit (128 × 8 or 64 × 16) low-voltage serial EEPROM with Microwire interface, ORG-pin-selectable memory organization, and 1.8V–5.5V single-supply operation. It delivers 70 µA typical active read current at 1.8V, 2 µA standby current, and supports 1,000,000 erase/write cycles with >200-year data retention. It is used in embedded system configuration storage, sensor calibration data logging, and power-sensitive industrial controllers.
For engineers reviewing the 93AA46XT/SN datasheet, 93AA46XT/SN pinout, 93AA46XT/SN application, or 93AA46XT/SN equivalent, key selection criteria include its 8-pin SOIC-SN package, 3-wire serial I/O compatibility, self-timed erase/write timing (4 ms/word), VCC=1.8V minimum programming voltage, and ORG-pin-configurable x8/x16 memory mapping.
Technical Context
The 93AA46XT/SN implements a synchronous 3-wire Microwire-compatible serial interface with CS, CLK, and bidirectional DI/DO lines. Its internal architecture includes an address counter, mode decode logic, clock generator, and output buffer, enabling sequential read and status polling via DO during erase/write operations.
Memory organization is dynamically selected by the ORG pin: tied to VCC for 64 × 16-bit mode or to VSS for 128 × 8-bit mode. All programming operations require prior execution of EWEN, and automatic ERAL precedes WRAL. Power-on/off protection inhibits writes below 1.4V VCC.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 1 Kbit (128 × 8 or 64 × 16 bits), selectable via ORG pin |
| Supply voltage | 1.8V to 5.5V - enables direct interfacing with 1.8V/3.3V/5V microcontrollers without level shifters |
| Active read current | 70 µA typical at 1.8V - supports ultra-low-power battery-backed applications |
| Standby current | 2 µA typical at 1.8V - minimizes quiescent power in always-on systems |
| Erase/write endurance | 1,000,000 cycles - ensures long-term reliability in frequent-update firmware/data storage |
| Data retention | >200 years at 25°C - guarantees nonvolatile integrity over product lifetime |
| Interface protocol | Industry-standard 3-wire Microwire - compatible with legacy and resource-constrained MCUs |
Pinout & Package
8-pin SOIC package per JEDEC MS-012 standard (narrow, 150 mil body), marked "/SN" per Microchip's packaging nomenclature. Pinout matches rotated layout for SN package only.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-high enable; must be held low ≥250 ns between instructions; initiates self-timed erase/write on falling edge |
| CLK | Serial Clock | Synchronizes opcode/address/data transfer on rising edge; stoppable mid-sequence; not required during auto-erase/write |
| DI | Data Input | Receives Start bit, opcode, address, and write data; supports shared DI/DO bus with pull-up (caution: potential bus conflict) |
| DO | Data Output / Status | Outputs read data or Ready/Busy status (low = busy); enters high-Z on CS falling edge |
| VSS | Ground | Reference return path for all signals and power; must be connected to system GND |
| ORG | Memory Organization | Selects 128×8 (ORG=VSS) or 64×16 (ORG=VCC); floating allowed only ≤1 MHz in x16 mode |
| NU | Not Utilized | No internal connection; must be left unconnected or tied to VSS/VCC per board layout best practice |
| VCC | Power Supply | 1.8V–5.5V supply; internal power-on reset and data protection activate at 1.4V threshold |
Key Features
| Feature | Design Value |
|---|---|
| Single-supply 1.8V programming | Eliminates need for charge pumps or external high-voltage generators in low-voltage systems |
| Self-timed erase/write cycles | Removes external timing control burden; simplifies firmware implementation of EEPROM access |
| Automatic ERAL before WRAL | Guarantees full-array erase prior to bulk write, preventing partial-write corruption |
| Power-on/off data protection | Hardware-enforced write inhibition outside 1.4V–5.5V VCC window prevents accidental data loss during brownout |
| Sequential read function | Enables efficient block reads with single CS assertion, reducing transaction overhead in configuration loading |
Applications
| Industrial Sensor Calibration Storage | Embedded System Configuration Memory |
|---|---|
Use Scenario: Storing factory-trimmed offset/gain coefficients for analog sensor front-ends in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed during boot or recalibration; interfaces via Microwire to host MCU. Use Value: Enables field-replaceable sensor modules with persistent calibration data across power cycles and firmware updates. | Use Scenario: Holding user-defined settings (e.g., display brightness, communication baud rate) in medical diagnostic equipment. IC Role / Device Role / Timing Role: Configuration EEPROM accessed infrequently but requiring guaranteed write integrity and low standby power. Use Value: Maintains critical operational parameters through 10+ year device lifespan with zero maintenance. |
| Low-Power IoT Node Data Logging | Legacy MCU Firmware Patch Storage |
Use Scenario: Recording timestamped environmental readings (temperature/humidity) in battery-powered wireless sensors. IC Role / Device Role / Timing Role: Low-energy data sink using 70 µA read and 2 µA standby current; triggered by MCU after ADC conversion. Use Value: Extends coin-cell battery life to >5 years while supporting 1M+ write cycles for daily log rotation. | Use Scenario: Storing hotfix patches or bootloader update flags in automotive body control modules with aging 8-bit MCUs. IC Role / Device Role / Timing Role: Microwire-compatible patch repository accessed during reset sequence; leverages existing 3-wire hardware. Use Value: Enables field-upgradable functionality without MCU replacement or PCB redesign. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93AA46C-I/SN | Same 1K-bit capacity and SOIC-SN package; updated revision with enhanced ESD rating (6 kV HBM vs. 4 kV) and extended temperature range (-40°C to +85°C) | Required for industrial environments with wider thermal cycling or higher electrostatic risk | Preferred for new designs where long-term availability and robustness are prioritized over legacy footprint compatibility |
| AT25010B-MAHL-T | 1K-bit SPI EEPROM (not Microwire); 2.5–5.5V supply; 5 MHz max clock; different instruction set and status polling method | Requires firmware adaptation for SPI protocol stack and command translation | Selected when migrating to SPI-based platforms or consolidating with other Atmel SPI peripherals |
Compared with 93AA46XT/SN, the 93AA46C-I/SN offers improved ruggedness and temperature support without changing pinout or software interface, while the AT25010B-MAHL-T provides higher speed and broader voltage tolerance at the cost of protocol migration effort.
Availability
93AA46XT/SN is available at Aetrix Electronics and suitable for industrial sensor calibration storage, embedded system configuration memory, and low-power IoT node data logging requiring stable component supply and long-term lifecycle support.
Supply support for 93AA46XT/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 93AAxx family was designed specifically for cost-sensitive, low-power embedded systems requiring simple, reliable serial nonvolatile memory with minimal external components and broad voltage compatibility.
FAQ
What is the memory organization flexibility of the 93AA46XT/SN?
The 93AA46XT/SN supports dual memory configurations via the ORG pin: connecting ORG to VSS selects 128 × 8-bit organization, while tying it to VCC selects 64 × 16-bit organization. This allows firmware to optimize data structure alignment without changing hardware. The 93AA46XT/SN does not support dynamic reconfiguration - the ORG state is sampled at power-up and remains fixed until reset.
How does the 93AA46XT/SN handle power transitions during write operations?
The 93AA46XT/SN incorporates hardware-level power-on/off data protection: write operations are automatically inhibited when VCC falls below 1.4V or rises above 5.5V. This prevents partial writes and data corruption during brownouts or unstable power ramp-up. The 93AA46XT/SN also requires explicit EWEN instruction before any erase/write, adding a software safeguard against accidental modification.
Can the 93AA46XT/SN be used with modern 3.3V or 5V microcontrollers?
Yes, the 93AA46XT/SN operates across 1.8V to 5.5V, making it fully compatible with 3.3V and 5V MCUs without level-shifting circuitry. Its VIH and VIL thresholds scale with VCC (e.g., VIH2 = 0.7 × VCC), ensuring reliable logic recognition. The 93AA46XT/SN maintains full AC timing compliance up to 2 MHz at VCC ≥ 4.5V and 1 MHz at lower voltages.
What is the role of the NU pin on the 93AA46XT/SN?
The NU (Not Utilized) pin on the 93AA46XT/SN has no internal connection and serves only as a mechanical placeholder in the 8-pin SOIC-SN package. It must remain unconnected in the circuit; tying it to VSS or VCC is unnecessary and may introduce unintended coupling paths. The 93AA46XT/SN datasheet explicitly states NU is not bonded internally.
Does the 93AA46XT/SN support sequential read across address boundaries?
Yes, the 93AA46XT/SN supports true sequential read: when CS remains asserted, each subsequent READ instruction automatically increments the internal address counter and outputs the next memory location's data. This eliminates the need to retransmit addresses for block reads, reducing transaction time and MCU overhead. The 93AA46XT/SN performs this in both x8 and x16 modes, wrapping correctly at the end of the array.
93AA46XT/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8, 64 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- -
- Voltage - Supply:
- 1.8V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
93AA46XT/SN FAQ
1.How can I place an order for 93AA46XT/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 93AA46XT/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93AA46XT/SN reliable?
The price and inventory of 93AA46XT/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93AA46XT/SN is usually 5 days.
3.What payment methods are accepted for 93AA46XT/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93AA46XT/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93AA46XT/SN?
93AA46XT/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93AA46XT/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93AA46XT/SN?
For technical support, including 93AA46XT/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93AA46XT/SN requirements.
6.How does Aetrix verify that 93AA46XT/SN is sourced from the original manufacturer or authorized distributors?
All 93AA46XT/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93AA46XT/SN meets industry standards.
7.What is the process for return or replacement of 93AA46XT/SN?
All 93AA46XT/SN units undergo pre-shipment inspection (PSI). If there is an issue with 93AA46XT/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93AA46XT/SN part is unused and in its original packaging.
Return procedure for 93AA46XT/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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