My Inquiry
My Account
Microchip Technology 93C46AT-I/SN
- Part No.:
- 93C46AT-I/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
93C46AT-I/SN.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:2,027
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
93C46AT-I/SN from Microchip Technology Inc. is a 1 Kbit (128 × 8-bit) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, 4.5–5.5 V supply range, and industrial temperature rating (–40°C to +85°C). It features self-timed erase/write cycles, automatic erase-all-before-write-all (ERAL/WRAL), power-on/off data protection, and Ready/Busy status signaling via DO pin. Used for configuration storage in embedded controllers, sensor calibration registers, and boot parameter retention.
For engineers reviewing the 93C46AT-I/SN datasheet, 93C46AT-I/SN pinout, 93C46AT-I/SN application, or 93C46AT-I/SN equivalent, key selection criteria include its fixed 8-bit organization (no ORG pin), 2 ms typical write cycle time, 1 million erase/write endurance, 200+ year data retention, and SOIC-8 (SN) package compatibility with legacy board layouts.
Technical Context
This device implements a synchronous serial Microwire protocol with start-bit detection, opcode-driven instruction set (READ, WRITE, ERASE, ERAL, WRAL, EWEN/EWDS), and hardware-level data protection via VCC voltage detect (3.8 V threshold). Communication requires CS high, CLK rising-edge sampling of DI, and DO-driven status polling during programming.
Unlike C-variant parts, the 93C46A has no ORG pin and operates exclusively in 8-bit mode; all instructions use 7-bit addressing (A6–A0) and 8-bit data payloads. Write initiation is triggered by the rising edge of CLK on the final data bit, distinguishing it from AA/LC variants that use CS falling edge.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Kbit (128 × 8-bit) - fixed x8 organization; no ORG pin; supports 128 distinct byte-addressable locations. |
| VCC Range | 4.5 V to 5.5 V - operation disabled below 3.8 V (VPOR threshold); not compatible with 3.3 V or 2.5 V systems. |
| Write Cycle Time | 2 ms typical - self-timed auto-erase-and-write; eliminates need for external timing control or busy-wait loops beyond DO polling. |
| Endurance | 1,000,000 erase/write cycles - specified at 25°C and VCC = 5.0 V; enables long-term field reprogramming in maintenance-critical applications. |
| Data Retention | >200 years - guaranteed nonvolatile data storage at +85°C; suitable for lifetime-critical configuration memory without refresh. |
| Interface | Microwire-compatible 3-wire serial (CS, CLK, DI/DO) - requires no I²C or SPI peripheral; minimal GPIO overhead on microcontrollers. |
| Temperature Range | –40°C to +85°C (Industrial grade) - validated across full range for reliable operation in industrial control and automotive under-hood modules. |
Pinout & Package
Package: 8-lead SOIC (SN), 3.9 mm × 4.9 mm body, 1.27 mm pitch, Pb-free Matte Tin finish. Pin 1 marked by laser dot or notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-high enable; must be held low ≥250 ns between instructions; initiates standby mode when low during active cycle. |
| CLK | Serial Clock | Rising-edge synchronized I/O; clocking stops freely during transmission; rising edge on final data bit triggers write cycle. |
| DI | Data Input | Accepts start bit, opcode (2 bits), address (7 bits), and data (8 bits); high-impedance when not selected. |
| DO | Data Output / Status | Outputs read data or Ready/Busy (low = busy); enters High-Z on CS falling edge; requires CS high ≥250 ns to sample status. |
| VSS | Ground | Reference for all logic and analog circuitry; must be low-impedance connection to minimize noise coupling into DO/CLK. |
| NC | No Internal Connection | Pin 7 is unconnected; must be left floating or tied to VSS per layout best practice; no internal bond wire. |
| VCC | Power Supply | 4.5–5.5 V only; internal POR circuit blocks operation below 3.8 V; decoupling capacitor (0.1 µF) required within 5 mm. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Erase/Write | Eliminates external timing circuitry; 2 ms typical cycle time ensures deterministic firmware delay budgeting. |
| Automatic ERAL before WRAL | Guarantees full-array readiness prior to bulk write; prevents partial writes and data corruption without host software intervention. |
| Power-On/Off Data Protection | VCC monitoring at 3.8 V disables all write operations during brown-out or ramp-up; prevents inadvertent writes during power transitions. |
| Ready/Busy Status via DO | Enables efficient polling instead of fixed delays; reduces CPU idle time and improves system responsiveness during configuration updates. |
| Industry Standard Microwire Interface | Compatible with legacy 8051, PIC, and ARM Cortex-M peripherals using bit-banged or hardware UART/SPI emulated modes. |
Applications
| Industrial PLC Configuration Storage | Automotive Sensor Calibration Memory |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and alarm thresholds in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed during boot and runtime via Microwire interface; retains values across power cycles. Use Value: Enables field-upgradable machine logic without firmware reflashing; 1M endurance supports decades of maintenance cycles. |
Use Scenario: Holding factory-trimmed offset/gain coefficients for temperature, pressure, and position sensors in engine control units. IC Role / Device Role / Timing Role: Calibration data repository read once at startup; write-protected during normal operation via EWDS command. Use Value: Maintains sensor accuracy over vehicle lifetime; >200-year retention exceeds automotive service life requirements. |
| Medical Device Boot Parameters | Consumer Appliance User Settings |
Use Scenario: Storing safety-critical boot flags, default operational modes, and regulatory compliance settings in infusion pumps and diagnostic monitors. IC Role / Device Role / Timing Role: Secure configuration store with power-fail write inhibition; accessed early in boot sequence before main MCU initialization. Use Value: Ensures deterministic startup behavior and regulatory traceability; POR lockout prevents corruption during AC line dropouts. |
Use Scenario: Retaining user preferences (temperature setpoints, cycle selections, language) across power loss in washing machines and HVAC controllers. IC Role / Device Role / Timing Role: Low-power nonvolatile memory interfaced to 8-bit microcontroller GPIO; written infrequently but read at every power-on. Use Value: Delivers seamless user experience with zero configuration loss; 5.5 V max VCC allows direct connection to 5 V rail without regulator. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC46AT-I/SN | Wider VCC range (2.5–5.5 V); same 8-bit organization; 6 ms write cycle; includes ORG pin (NC on A-version). | Supports 3.3 V systems; slower write timing increases firmware latency; identical pinout and instruction set. | Select when operating below 4.5 V or requiring dual-voltage design flexibility; verify timing margins for 3.3 V CLK/DI drive levels. |
| AT25010B-MAHL-T | SPI interface (4-wire), 1.8–5.5 V, 5 ms write cycle, 1 M endurance, same 1 Kbit density; no Ready/Busy pin - uses WIP flag polling. | Requires SPI peripheral or bit-bang implementation; lacks dedicated status pin; higher pin count (SOIC-8 with HOLD/ WP). | Choose for SPI-native designs or where write-protection (WP pin) and hold functionality are required; rework needed for Microwire-to-SPI translation. |
Compared with 93LC46AT-I/SN and AT25010B-MAHL-T, the 93C46AT-I/SN offers fastest write speed (2 ms) and strictest VCC stability (3.8 V POR), making it optimal for 5 V-only industrial systems where timing determinism and power-rail integrity are critical.
Availability
93C46AT-I/SN is available at Aetrix Electronics and suitable for industrial PLC configuration storage, automotive sensor calibration memory, and medical device boot parameters requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.
Supply support for 93C46AT-I/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, mixed-signal, analog, and Flash-IP solutions, headquartered in Chandler, Arizona, with global design, manufacturing, and sales operations.
The 93Cxx EEPROM family was designed for cost-sensitive, low-pin-count embedded systems requiring reliable nonvolatile storage with minimal MCU resource usage and robust power-fail immunity.
FAQ
What is the function of the NC pin on the 93C46AT-I/SN?
The NC (No Connection) pin on the 93C46AT-I/SN is Pin 7 in the SOIC-8 package and has no internal bond wire or circuit connection. It must be left electrically floating or tied to VSS per PCB layout best practices to avoid parasitic coupling. This pin corresponds to the ORG pin on C-variant devices but is unassigned in the 93C46A series, which uses fixed 8-bit organization.
Does the 93C46AT-I/SN support 3.3 V operation?
No, the 93C46AT-I/SN does not support 3.3 V operation. Its absolute minimum VCC is 4.5 V, and its power-on reset (POR) circuit disables all functions below 3.8 V. Attempting to operate at 3.3 V will result in undefined behavior, failed writes, and potential data corruption. For 3.3 V systems, consider the 93LC46AT-I/SN instead.
How is the Ready/Busy status read on the 93C46AT-I/SN?
The Ready/Busy status on the 93C46AT-I/SN is signaled via the DO pin: logic low indicates an ongoing erase or write cycle, while logic high confirms completion. To sample status, CS must be brought high for ≥250 ns after the TCSL interval, then the DO level is read on the next CLK rising edge. The DO pin returns to High-Z on CS falling edge.
What is the difference between 93C46AT-I/SN and 93C46BT-I/SN?
The 93C46AT-I/SN provides 128 × 8-bit (x8) organization with fixed byte-wide access, while the 93C46BT-I/SN offers 64 × 16-bit (x16) organization for word-wide access. Both share identical VCC range (4.5–5.5 V), package (SOIC-8), and timing (2 ms write), but differ in address width (7-bit vs. 6-bit), data bus width (8-bit vs. 16-bit), and instruction set operand size.
Is an EWEN command required before every write operation on the 93C46AT-I/SN?
Yes - the 93C46AT-I/SN powers up in Erase/Write Disable (EWDS) mode. An EWEN (Erase/Write Enable) instruction must be issued before any ERASE, WRITE, ERAL, or WRAL command. After successful execution, programming remains enabled until EWDS is sent or VCC is cycled. This prevents accidental writes during noise events or power transients.
93C46AT-I/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 2ms
- Access Time:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
93C46AT-I/SN FAQ
1.How can I place an order for 93C46AT-I/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 93C46AT-I/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93C46AT-I/SN reliable?
The price and inventory of 93C46AT-I/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93C46AT-I/SN is usually 5 days.
3.What payment methods are accepted for 93C46AT-I/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93C46AT-I/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93C46AT-I/SN?
93C46AT-I/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93C46AT-I/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93C46AT-I/SN?
For technical support, including 93C46AT-I/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93C46AT-I/SN requirements.
6.How does Aetrix verify that 93C46AT-I/SN is sourced from the original manufacturer or authorized distributors?
All 93C46AT-I/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93C46AT-I/SN meets industry standards.
7.What is the process for return or replacement of 93C46AT-I/SN?
All 93C46AT-I/SN units undergo pre-shipment inspection (PSI). If there is an issue with 93C46AT-I/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93C46AT-I/SN part is unused and in its original packaging.
Return procedure for 93C46AT-I/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
93C46AT-I/SN Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
