Microchip Technology 93C46B-I/P
- Part No.:
- 93C46B-I/P
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
93C46B-I/P.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8DIP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
93C46B-I/P from Microchip Technology Inc. is a 1Kbit (64 × 16-bit) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, 4.5–5.5 V supply range, and industrial temperature rating (–40°C to +85°C). It features self-timed erase/write cycles, automatic ERAL/WRAL support, Ready/Busy status via DO pin, and 1,000,000 endurance cycles. Used for configuration storage in embedded controllers and power management ICs.
For engineers reviewing the 93C46B-I/P datasheet, 93C46B-I/P pinout, 93C46B-I/P application, or 93C46B-I/P equivalent, key selection considerations include its fixed 16-bit word organization, absence of ORG pin (NC), PDIP-8 package compatibility, VCC-dependent write timing (2 ms), and RoHS-compliant matte tin finish.
Technical Context
The 93C46B-I/P implements a synchronous serial Microwire interface with CS, CLK, DI, and DO signals - no ORG pin required, as it is permanently configured for 64 × 16-bit memory mapping. All instructions (READ, WRITE, ERASE, ERAL, WRAL, EWEN/EWDS) are initiated by a Start bit followed by opcode and address/data on rising CLK edges.
Write operations use auto-erase-before-write architecture and are initiated by the rising edge of CLK on the final data bit (93C-series behavior). Device enters Standby mode when CS is low, with ICCS ≤ 5 µA at I-temp; power-on reset disables writes until EWEN is issued.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Kbit (64 words × 16 bits) - supports compact firmware parameter storage without external address latching |
| VCC Range | 4.5 V to 5.5 V - compatible with legacy 5 V logic systems; POR threshold at 3.8 V prevents spurious writes during brown-out |
| Interface | Microwire 3-wire serial (CS/CLK/DI/DO) - requires only four GPIOs; no SPI mode or dual I/O |
| Write Cycle Time | 2 ms typical (TWC) - enables fast field updates; no external delay needed beyond CS timing constraints |
| Endurance | 1,000,000 erase/write cycles - suitable for dynamic calibration data logging in industrial sensors |
| Data Retention | 200 years at +25°C - ensures long-term reliability in unattended equipment like utility meters |
| Temperature Range | –40°C to +85°C (Industrial grade) - validated across full range for automotive body control modules |
Pinout & Package
Package: 8-lead PDIP (Plastic Dual In-line Package), Pb-free matte tin finish, 0.3 inch body width, through-hole mountable.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 CS | Chip Select | Active-high enable; must be held low ≥250 ns between instructions; resets internal logic when low |
| 2 CLK | Serial Clock | Rising-edge synchronized I/O; clocking stops during self-timed write; TCKH/TCKL defined per VCC |
| 3 DI | Data Input | Accepts Start bit, opcodes, addresses, and write data; high-impedance when not selected |
| 4 DO | Data Output / Status | Outputs read data or Ready/Busy (low = busy); enters High-Z on CS falling edge |
| 5 VSS | Ground | Reference for all I/O and internal circuitry; decoupling capacitor required near pin |
| 6 NC | No Internal Connection | Not bonded; must be left floating or tied to VSS - no functionality or signal routing |
| 7 NC | No Internal Connection | Not bonded; identical constraint as Pin 6; unused in 93C46B variant |
| 8 VCC | Power Supply | 4.5–5.5 V supply; internal voltage detector (VPOR = 3.8 V) blocks writes below threshold |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Erase/Write | Eliminates need for external timing control or polling delays beyond DO status check |
| Automatic ERAL before WRAL | Ensures full array is erased prior to bulk write - no separate ERAL command required |
| Power-On/Off Data Protection | Hardware-level write inhibition below 3.8 V VCC prevents corruption during power ramp |
| Ready/Busy via DO pin | Enables real-time status monitoring without additional pins or interrupt lines |
| Sequential Read Mode | Reduces host CPU overhead: holding CS high automatically increments address after each byte/word |
| RoHS Compliant Matte Tin Finish | Meets lead-free assembly requirements for reflow soldering and environmental compliance |
Applications
| Industrial Sensor Calibration | Embedded Controller Configuration |
|---|---|
Use Scenario: Storing temperature-compensated offset/gain coefficients in a pressure transducer. IC Role / Device Role / Timing Role: Nonvolatile parameter storage accessed during power-up initialization and runtime recalibration. Use Value: 200-year data retention ensures calibration remains valid over product lifetime without battery backup. |
Use Scenario: Holding boot configuration flags (e.g., UART baud rate, I²C address, watchdog timeout) in a PLC CPU module. IC Role / Device Role / Timing Role: Serial configuration memory interfaced directly to MCU GPIOs using minimal firmware drivers. Use Value: 2 ms write time allows rapid field updates during maintenance without halting system operation. |
| Power Supply Sequencing Logic | Automotive Body Control Module |
Use Scenario: Storing startup delay values and rail-enable thresholds in an AC/DC power management ASIC. IC Role / Device Role / Timing Role: Dedicated configuration store for analog power sequencing controller with 5 V supply domain. Use Value: 4.5–5.5 V VCC range matches primary bias rail, eliminating level-shifting components. |
Use Scenario: Saving seat position memory and mirror angle presets in a vehicle door module. IC Role / Device Role / Timing Role: Industrial-grade EEPROM interfaced to 8-bit microcontroller over Microwire bus. Use Value: –40°C to +85°C rating ensures reliable operation in under-hood and door cavity environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC46B-I/P | Wider VCC range (2.5–5.5 V); same 64×16 organization and PDIP-8 package | Supports 3.3 V and 5 V systems; lacks 93C's higher VCC noise immunity | Select for mixed-voltage designs where 5 V margin is not critical |
| AT25010B-PU | SPI interface (4-wire), 1 Kbit (128×8), 1.8–5.5 V, 5 ms write time | Requires SPI peripheral instead of GPIO-bitbanged Microwire; different instruction set | Choose when existing SPI infrastructure exists and 8-bit word access suffices |
Compared with 93LC46B-I/P, the 93C46B-I/P offers tighter VCC noise margin but less voltage flexibility; versus AT25010B-PU, it uses simpler 3-wire control and delivers faster writes, though requiring custom Microwire driver code.
Availability
93C46B-I/P is available at Aetrix Electronics and suitable for industrial sensor calibration, embedded controller configuration, and power supply sequencing applications requiring stable component supply, long-lifecycle support, and RoHS-compliant through-hole packaging.
Supply support for 93C46B-I/P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and nonvolatile memory solutions, headquartered in Chandler, Arizona.
The 93Cxx series was designed specifically for cost-sensitive, low-pin-count embedded systems needing reliable serial EEPROM with Microwire compatibility and robust power-supply immunity.
FAQ
What is the memory organization of the 93C46B-I/P?
The 93C46B-I/P has a fixed 64 × 16-bit organization - 64 words of 16 bits each, totaling 1,024 bits. Unlike 'C' variants, it has no ORG pin; the 16-bit width is hardwired. This eliminates external configuration logic and simplifies host software for word-aligned data access. The 93C46B-I/P does not support 8-bit mode.
Does the 93C46B-I/P require an external pull-up resistor on the DO pin?
No, the 93C46B-I/P does not require an external pull-up on DO. The DO pin actively drives high/low during READ and Ready/Busy status reporting, and enters High-Z when CS is low or during non-read operations. A pull-up may interfere with correct status detection and is not recommended per Microchip's design guidelines for the 93C46B-I/P.
How is write protection implemented on the 93C46B-I/P?
Write protection on the 93C46B-I/P is implemented via hardware POR lockout (below 3.8 V VCC) and software-controlled EWEN/EWDS commands. The device powers up in EWDS (Erase/Write Disable) state. An EWEN instruction must precede any ERASE or WRITE operation, and issuing EWDS afterward relocks the memory. This two-layer scheme prevents accidental writes during power transitions or firmware glitches in the 93C46B-I/P.
Can the 93C46B-I/P be used in a 3.3 V system?
No, the 93C46B-I/P is not rated for 3.3 V operation. Its specified VCC range is strictly 4.5 V to 5.5 V, with a power-on reset threshold of 3.8 V. Attempting to operate the 93C46B-I/P at 3.3 V will result in undefined behavior, failed writes, and potential data corruption. For 3.3 V systems, consider the 93LC46B-I/P instead.
What is the maximum clock frequency supported by the 93C46B-I/P?
The 93C46B-I/P supports a maximum clock frequency of 3 MHz when VCC is 4.5 V to 5.5 V. Timing parameters such as TCKH (200 ns min), TCKL (100 ns min), and TDIS/TDIH (50 ns min) are guaranteed across this range. Exceeding 3 MHz violates AC specifications and risks command misinterpretation or incomplete data latching in the 93C46B-I/P.
93C46B-I/P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 64 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 2ms
- Access Time:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
93C46B-I/P FAQ
1.How can I place an order for 93C46B-I/P through Aetrix?
Please submit a Request for Quotation (RFQ) for 93C46B-I/P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93C46B-I/P reliable?
The price and inventory of 93C46B-I/P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93C46B-I/P is usually 5 days.
3.What payment methods are accepted for 93C46B-I/P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93C46B-I/P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93C46B-I/P?
93C46B-I/P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93C46B-I/P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93C46B-I/P?
For technical support, including 93C46B-I/P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93C46B-I/P requirements.
6.How does Aetrix verify that 93C46B-I/P is sourced from the original manufacturer or authorized distributors?
All 93C46B-I/P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93C46B-I/P meets industry standards.
7.What is the process for return or replacement of 93C46B-I/P?
All 93C46B-I/P units undergo pre-shipment inspection (PSI). If there is an issue with 93C46B-I/P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93C46B-I/P part is unused and in its original packaging.
Return procedure for 93C46B-I/P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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