Microchip Technology 93C46BXT-I/SN
- Part No.:
- 93C46BXT-I/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
93C46BXT-I/SN.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
93C46BXT-I/SN from Microchip Technology Inc. is a 1Kbit (64 × 16-bit) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, 4.5–5.5 V supply range, and industrial temperature grade (−40°C to +85°C). It features self-timed erase/write cycles, automatic ERAL before WRAL, Ready/Busy status via DO pin, and 1,000,000 endurance cycles. Used for configuration storage in embedded controllers and power management ICs.
For engineers reviewing the 93C46BXT-I/SN datasheet, 93C46BXT-I/SN pinout, 93C46BXT-I/SN application, or 93C46BXT-I/SN equivalent, key selection considerations include its fixed 16-bit organization (no ORG pin), SOIC-8 package, 2 ms program cycle time, VCC ≥4.5 V requirement for ERAL/WRAL, and compatibility with legacy Microwire host controllers requiring dedicated x16 data width.
Technical Context
The 93C46BXT-I/SN implements a synchronous serial interface with CS, CLK, and DI/DO pins, operating exclusively in 16-bit mode without ORG pin functionality (as confirmed for 'B' variants). Its internal architecture includes an address decoder, data register, and output buffer, with all programming initiated by CLK rising edge on final data bit - distinct from 'A'/'C' variants that use CS falling edge.
It supports full memory operations including READ (18-clock cycle), WRITE (18-clock), ERASE (10-clock), ERAL (10-clock), and WRAL (18-clock), all requiring prior EWEN command and VCC ≥4.5 V for bulk operations. Power-on data protection is enforced via VCC detect threshold of 3.8 V, disabling writes below that level.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Kbit (64 words × 16 bits); provides compact nonvolatile storage for calibration tables or device IDs in space-constrained designs. |
| Supply Voltage | 4.5–5.5 V; requires stable regulated rail - incompatible with 3.3 V or battery-backed systems without level shifting. |
| Interface | Microwire-compatible 3-wire serial (CS, CLK, DI/DO); no SPI mode or dual I/O - mandates host controller support for Microwire timing and instruction set. |
| Write Cycle Time | 2 ms typical (TWC); enables fast firmware updates without long blocking delays during configuration writes. |
| Endurance | 1,000,000 erase/write cycles; suitable for applications requiring frequent parameter logging or field-updatable settings. |
| Data Retention | 200 years at 25°C; ensures long-term reliability for products with multi-decade service life expectations. |
| Temperature Range | −40°C to +85°C (Industrial grade); validated for operation in industrial control panels and automotive under-hood modules. |
Pinout & Package
93C46BXT-I/SN is packaged in 8-lead SOIC (SN) with standard pinout and Pb-free Matte Tin finish. Pin 1 is CS, Pin 2 is CLK, Pin 3 is DI, Pin 4 is DO, Pin 5 is VSS, Pin 6 is NC (no internal connection), Pin 7 is NC, and Pin 8 is VCC. The ORG pin is absent - consistent with 'B'-suffix devices configured exclusively for 16-bit operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS (Pin 1) | Chip Select | Active-high enable; must be held low ≥250 ns between instructions; deselects device into standby but allows ongoing write completion. |
| CLK (Pin 2) | Serial Clock | Synchronizes all data transfers; rising edge clocks in opcode/address/data; stopped clock allowed pre-start condition. |
| DI (Pin 3) | Data Input | Receives Start bit, opcodes, addresses, and write data; shares bidirectional bus with DO only with external current-limiting resistor. |
| DO (Pin 4) | Data Output / Status | Outputs read data or Ready/Busy status (low = busy); enters High-Z when CS is low or during non-read states. |
| VSS (Pin 5) | Ground | Reference for all logic and analog circuitry; must be low-impedance connection to minimize noise coupling into DO timing. |
| NC (Pin 6 & 7) | No Connection | Unbonded die pads; must remain unconnected - floating or tied to VSS/VCC may cause latch-up or ESD vulnerability. |
| VCC (Pin 8) | Power Supply | 4.5–5.5 V input; internal POR triggers at 3.8 V; bulk operations (ERAL/WRAL) require ≥4.5 V to function reliably. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Erase/Write | Eliminates need for external timing control - host processor can poll DO pin or insert fixed 2 ms delay after WRITE/ERASE initiation. |
| Automatic ERAL before WRAL | Ensures clean memory state before bulk write; removes requirement for separate ERAL command in configuration initialization sequences. |
| Ready/Busy Status on DO | Enables efficient polling-based write handling without fixed delays - reduces average write latency in interrupt-driven systems. |
| Power-On/Off Data Protection | VCC detect at 3.8 V blocks all write operations during brown-out or power ramp-up, preventing corruption during unstable supply conditions. |
| 1,000,000 Endurance Cycles | Supports daily reconfiguration over 27 years - sufficient for factory calibration, field firmware patching, and adaptive tuning applications. |
Applications
| Industrial PLC Configuration Storage | Automotive Body Control Module (BCM) Settings |
|---|---|
Use Scenario: Storing I/O mapping tables, PID tuning parameters, and calibration offsets in programmable logic controllers. IC Role / Device Role / Timing Role: Nonvolatile configuration memory interfaced to microcontroller's Microwire peripheral; accessed during boot and runtime parameter updates. Use Value: Ensures deterministic startup behavior and retains user-defined logic configurations across power cycles without external backup power. |
Use Scenario: Holding door lock logic states, mirror position presets, and lighting dimming profiles in automotive BCMs. IC Role / Device Role / Timing Role: Dedicated 16-bit serial EEPROM providing robust storage for safety-critical vehicle personalization data. Use Value: Meets AEC-Q100 stress requirements for industrial temp range and delivers 200-year data retention for lifetime vehicle ownership. |
| Legacy Industrial Instrumentation Calibration | Power Supply Digital Control Register Backup |
Use Scenario: Saving sensor gain/offset coefficients and linearity correction tables in analog multimeters and oscilloscopes. IC Role / Device Role / Timing Role: Microwire EEPROM directly connected to 8051 or similar legacy MCU with native Microwire support. Use Value: Maintains traceable calibration history without requiring firmware changes - compatible with decades-old test equipment designs. |
Use Scenario: Backing up digital PWM duty cycle registers and voltage reference trim values in digitally controlled AC/DC power supplies. IC Role / Device Role / Timing Role: Nonvolatile shadow memory for digital power controller state, updated only during factory programming or field recalibration. Use Value: Guarantees safe power-up defaults and preserves fine-tuned regulation parameters even after extended storage or shipping. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93C46AXT-I/SN | Fixed 8-bit organization (64 × 8-bit), same SOIC-8 package and 4.5–5.5 V range; identical timing and instruction set except for 18-clock READ/WRITE addressing 7-bit address space. | Requires host software adaptation for byte-aligned access; unsuitable where 16-bit word storage is mandated by protocol or legacy driver. | Select when system uses 8-bit data paths or needs higher density per clock cycle in byte-oriented protocols. |
| AT25010B-MAUM-T | SPI interface (4-wire), 1 Kbit (128 × 8-bit), 1.8–5.5 V supply, 5 MHz max clock; lacks ERAL/WRAL and Ready/Busy pin - relies on WIP flag polling. | Requires SPI master instead of Microwire; no hardware status pin - increases software overhead for write completion detection. | Select when migrating to modern SPI infrastructure or needing wider VCC range and lower quiescent current (5 µA vs. 1 µA standby). |
Compared with 93C46AXT-I/SN, the 93C46BXT-I/SN offers native 16-bit word storage ideal for parameter pairs, while AT25010B-MAUM-T provides SPI compatibility and broader voltage support but removes hardware-ready signaling and bulk-erase automation.
Availability
93C46BXT-I/SN is available at Aetrix Electronics and suitable for industrial PLCs, automotive body control modules, and legacy instrumentation requiring stable component supply with guaranteed long-term availability and RoHS-compliant packaging.
Supply support for 93C46BXT-I/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 93Cxx series was designed specifically for cost-sensitive, low-power embedded systems requiring reliable nonvolatile storage with minimal pin count and legacy Microwire compatibility - targeting industrial, automotive, and consumer applications.
FAQ
What is the memory organization of the 93C46BXT-I/SN?
The 93C46BXT-I/SN has a fixed 64-word × 16-bit (1 Kbit) organization. As a 'B'-suffix device, it does not include an ORG pin and operates exclusively in 16-bit mode - unlike 'C' variants which support configurable x8/x16 via the ORG pin. This makes it ideal for systems requiring native 16-bit data storage without external logic.
Does the 93C46BXT-I/SN support SPI communication?
No, the 93C46BXT-I/SN implements a Microwire-compatible 3-wire serial interface (CS, CLK, DI/DO) and is not SPI-compatible. It lacks the SI/SO pins and mode-select logic required for SPI. Host controllers must implement Microwire timing, instruction encoding, and 18-clock READ/WRITE sequences per the DS20001749K datasheet.
What is the minimum VCC required for ERAL and WRAL operations on the 93C46BXT-I/SN?
The 93C46BXT-I/SN requires VCC ≥ 4.5 V for proper execution of ERAL (Erase All) and WRAL (Write All) commands. Below this threshold, these bulk operations will fail silently - the device remains in EWDS mode and ignores the instruction. This is enforced by internal voltage detection circuitry with a 3.8 V POR threshold.
How is write completion signaled on the 93C46BXT-I/SN?
Write completion is signaled via the DO pin acting as a Ready/Busy status line. After initiating WRITE, ERASE, ERAL, or WRAL, the host must bring CS high for ≥250 ns (TCSL), then sample DO: logic low indicates ongoing operation, logic high confirms completion. DO returns to High-Z when CS is low.
Is the 93C46BXT-I/SN pin-compatible with other 93C46 variants in SOIC-8 package?
Yes - the 93C46BXT-I/SN shares identical SOIC-8 pinout (SN) with 93C46AXT-I/SN and 93C46CXT-I/SN, including CS (1), CLK (2), DI (3), DO (4), VSS (5), NC (6,7), and VCC (8). However, functional compatibility requires matching organization: 'A' (x8), 'B' (x16), or 'C' (configurable) - mixing variants without firmware adjustment causes data misalignment.
93C46BXT-I/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 64 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 2ms
- Access Time:
- -
- Voltage - Supply:
- 4.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
93C46BXT-I/SN FAQ
1.How can I place an order for 93C46BXT-I/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 93C46BXT-I/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93C46BXT-I/SN reliable?
The price and inventory of 93C46BXT-I/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93C46BXT-I/SN is usually 5 days.
3.What payment methods are accepted for 93C46BXT-I/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93C46BXT-I/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93C46BXT-I/SN?
93C46BXT-I/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93C46BXT-I/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93C46BXT-I/SN?
For technical support, including 93C46BXT-I/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93C46BXT-I/SN requirements.
6.How does Aetrix verify that 93C46BXT-I/SN is sourced from the original manufacturer or authorized distributors?
All 93C46BXT-I/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93C46BXT-I/SN meets industry standards.
7.What is the process for return or replacement of 93C46BXT-I/SN?
All 93C46BXT-I/SN units undergo pre-shipment inspection (PSI). If there is an issue with 93C46BXT-I/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93C46BXT-I/SN part is unused and in its original packaging.
Return procedure for 93C46BXT-I/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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