My Inquiry
My Account
Microchip Technology 93LC46AT-I/MC
- Part No.:
- 93LC46AT-I/MC
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-VFDFN Exposed Pad
- Datasheet:
-
93LC46AT-I/MC.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8DFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,470
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
93LC46AT-I/MC from Microchip Technology is a 1Kbit (128 × 8-bit) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, 2.5–5.5 V supply range, and industrial temperature rating (–40°C to +85°C). It features self-timed erase/write cycles, automatic ERAL before WRAL, power-on/off data protection, and Ready/Busy status signaling via DO pin - deployed in embedded system configuration storage, sensor calibration memory, and firmware parameter retention.
For engineers reviewing the 93LC46AT-I/MC datasheet, 93LC46AT-I/MC pinout, 93LC46AT-I/MC application, or 93LC46AT-I/MC equivalent, key selection criteria include its 8-bit fixed organization (no ORG pin), DFN-8 (2×3 mm) Pb-free package, 1 million erase/write endurance, 200-year data retention, and compatibility with microcontroller SPI-like serial masters requiring nonvolatile memory with hardware write protection.
Technical Context
The 93LC46AT-I/MC implements a synchronous serial Microwire protocol with CS, CLK, and DI/DO signals - no ORG pin (dedicated 8-bit x128 organization). It uses CMOS EEPROM technology with on-chip charge pump for internal high-voltage generation during erase/write, eliminating external VPP.
Operation requires an EWEN command to enable programming; it powers up in EWDS (Erase/Write Disable) state. Read, erase, write, ERAL, and WRAL instructions are executed via 10- or 18-clock-cycle sequences depending on operation, with DO pin providing real-time Ready/Busy status after CS reassertion post-TCSL (≥250 ns).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory Size | 1 Kbit (128 words × 8 bits) - fixed x8 organization; no ORG pin; no word-size configuration required. |
| VCC Range | 2.5 V to 5.5 V - supports wide-range microcontroller I/O domains; POR threshold at 1.5 V prevents spurious writes during brown-out. |
| Interface | Microwire-compatible 3-wire serial (CS, CLK, DI/DO) - software-bitbangable; no separate chip-select decoding logic needed. |
| Endurance | 1,000,000 erase/write cycles - validated at 25°C, 5.0 V; enables long-term field calibration updates in industrial sensors. |
| Data Retention | >200 years at 25°C - ensures lifetime data integrity in unpowered storage without refresh. |
| Max Clock Frequency | 3 MHz at VCC ≥4.5 V; 2 MHz at 2.5 V ≤ VCC <4.5 V - defines minimum instruction execution time (e.g., WRITE = 18 clocks + TWC = 6 ms). |
| Write Cycle Time | 6 ms typical (TWC) - self-timed; eliminates need for external timing control or polling delay estimation. |
| Operating Temp | –40°C to +85°C (Industrial grade) - qualified for use in motor controllers, HVAC modules, and industrial HMIs. |
Pinout & Package
93LC46AT-I/MC is housed in an 8-lead 2×3 mm DFN (Dual Flat No-lead) package with exposed pad (Pb-free Matte Tin finish). Pin 1 is laser-marked; exposed pad may be connected to VSS or left floating per Microchip packaging spec.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CS) | Chip Select | Active-high enable; must be held low ≥250 ns between instructions; deselects device into standby (ICCS ≤1 µA). |
| 2 (CLK) | Serial Clock | Synchronizes all data transfers; rising edge clocks in opcode/address/data; stoppable mid-sequence without error. |
| 3 (DI) | Data Input | Accepts Start bit, opcodes, addresses, and write data; tied to DO only with series resistor to avoid bus conflict. |
| 4 (DO) | Data Output / Status | Outputs read data or Ready/Busy (low = busy); enters High-Z when CS goes low; status valid only after CS high ≥TCSL. |
| 5 (NC) | No Internal Connection | Not bonded; must be left unconnected or tied to VSS/VCC per PCB layout best practice (no functional impact). |
| 6 (VSS) | Ground | Reference for all I/O and internal circuitry; recommended connection to exposed pad for thermal and noise performance. |
| 7 (ORG) | Organization | Not present - 93LC46A devices have NC at this position; fixed 8-bit mode; no external logic required. |
| 8 (VCC) | Power Supply | 2.5–5.5 V supply; internal voltage detector (VPOR = 1.5 V) blocks operations below threshold. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed erase/write | Eliminates external timing components and software delay loops; TWC = 6 ms guaranteed across temp/voltage. |
| Automatic ERAL before WRAL | Ensures full array erase prior to bulk write - prevents partial-write corruption without host MCU intervention. |
| Power-on/off data protection | Hardware lockout below VPOR (1.5 V) prevents inadvertent writes during power ramp-up/down or brown-out. |
| Ready/Busy status on DO | Enables efficient polling instead of fixed delays; reduces average write latency by up to 40% in interrupt-driven systems. |
| 1M endurance >200-yr retention | Validated for >10 years of daily calibration updates in battery-backed metering and telemetry applications. |
| RoHS-compliant Pb-free DFN | 2×3 mm footprint saves board space vs. SOIC-8; exposed pad improves thermal dissipation in sealed enclosures. |
Applications
| Smart Sensor Calibration Storage | Industrial PLC Configuration Memory |
|---|---|
Use Scenario: Storing factory-trimmed offset/gain coefficients and temperature compensation tables in MEMS pressure sensors. IC Role / Device Role / Timing Role: Nonvolatile parameter register accessed at power-up and during field recalibration; serial interface minimizes GPIO usage on low-pin-count MCUs. Use Value: Enables single-device calibration traceability; 1M endurance supports >200 recalibrations over product lifetime without wear-out risk. |
Use Scenario: Retaining user-defined I/O mapping, PID loop parameters, and alarm thresholds in DIN-rail mounted PLC modules. IC Role / Device Role / Timing Role: System configuration store updated infrequently but requiring guaranteed persistence across 10+ year deployments. Use Value: Eliminates battery-backed SRAM; 200-year retention ensures data survival beyond mechanical end-of-life. |
| Medical Device Setup Parameters | Consumer Appliance User Preferences |
Use Scenario: Saving clinician-configured therapy settings (e.g., flow rate limits, alarm thresholds) in portable infusion pumps. IC Role / Device Role / Timing Role: Secure, tamper-resistant storage accessible only after authentication; powered from main 3.3 V rail. Use Value: Meets IEC 62304 Class B software requirements for persistent data integrity; no external write-enable logic needed. |
Use Scenario: Preserving user-selected modes (e.g., eco, turbo), timer values, and language preferences in smart washing machines. IC Role / Device Role / Timing Role: Low-power background storage updated during idle cycles; accessed at boot and UI interaction. Use Value: DFN-8 package fits tight space constraints behind control panel; 2.5 V min VCC allows direct connection to 3.3 V LDO without level shifters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC46B-I/MC | 16-bit (64 × 16) organization; same VCC/temp/package; no ORG pin - fixed x16 mode. | Requires MCU firmware adaptation for 16-bit word access; incompatible with existing 8-bit read/write routines. | Select only if system architecture mandates 16-bit data alignment and memory bandwidth optimization. |
| AT25010B-MAHL-T | SPI interface (4-wire), 1 Kbit (128 × 8), 1.8–5.5 V, SOIC-8 package; no Ready/Busy pin - relies on WIP flag polling. | Larger footprint; requires extra GPIO for CS; lacks hardware status signal - increases MCU overhead during writes. | Choose when SPI-native MCU integration simplifies firmware, and DFN size is not critical. |
Compared with 93LC46B-I/MC, the 93LC46AT-I/MC offers native 8-bit compatibility and identical timing behavior; versus AT25010B-MAHL-T, it delivers lower pin count, smaller DFN-8 footprint, and deterministic Ready/Busy signaling - reducing both PCB area and firmware complexity in resource-constrained designs.
Availability
93LC46AT-I/MC is available at Aetrix Electronics and suitable for industrial automation, medical instrumentation, and consumer appliance designs requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for 93LC46AT-I/MC includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog, FPGA, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 93LC46A/B/C series was designed specifically for cost-sensitive, low-power embedded systems needing reliable, small-footprint serial EEPROM - emphasizing ease of integration, robustness across voltage/temperature, and long-term data integrity without batteries or capacitors.
FAQ
What is the memory organization of the 93LC46AT-I/MC?
The 93LC46AT-I/MC has a fixed 128 × 8-bit (1 Kbit) organization with no ORG pin - it operates exclusively in x8 mode. Unlike 'C' variants, it does not support runtime word-size switching; address range is A6–A0 (7 bits), and each READ/WRITE accesses one byte. This simplifies firmware implementation in 8-bit MCU environments.
Does the 93LC46AT-I/MC require an external pull-up resistor on the DO pin?
No - the 93LC46AT-I/MC DO pin has an active push-pull output during READ and Ready/Busy status reporting. External pull-ups are unnecessary and may cause contention. When CS is low, DO enters High-Z state; during status polling, DO drives low (busy) or high (ready) actively - verified in DS20001749K Figures 2-1, 2-7, and 2-8.
How is write protection implemented on the 93LC46AT-I/MC?
Write protection is enforced through dual hardware/software mechanisms: (1) Power-on reset places the 93LC46AT-I/MC in EWDS (Erase/Write Disable) mode, blocking all programming until EWEN is issued; (2) VPOR circuitry disables all instructions when VCC falls below ~1.5 V. Both features are intrinsic to the 93LC46AT-I/MC silicon - no external components required.
Can the 93LC46AT-I/MC be used with a 1.8 V microcontroller?
No - the 93LC46AT-I/MC specifies a minimum VCC of 2.5 V (see Device Selection Table, DS20001749K page 2). While 93AA46A supports 1.8 V, the 'LC' prefix denotes 2.5–5.5 V operation. Using it below 2.5 V risks incomplete writes, data corruption, or failure to recognize commands; always verify VCC against the 'LC' row in the selection table.
What is the purpose of the NC pin (Pin 5) on the 93LC46AT-I/MC DFN package?
Pin 5 on the 93LC46AT-I/MC is designated NC (No Connection) - it is not internally bonded and carries no electrical function. Per Microchip's package drawing (DS20001749K page 26), it may be left floating or tied to VSS/VCC for mechanical stability or ESD mitigation, but it must never be driven or used as a signal path. Its presence maintains pin compatibility across the 93XX46 family's DFN variants.
93LC46AT-I/MC Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-VFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 6ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-DFN (2x3)
93LC46AT-I/MC FAQ
1.How can I place an order for 93LC46AT-I/MC through Aetrix?
Please submit a Request for Quotation (RFQ) for 93LC46AT-I/MC on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93LC46AT-I/MC reliable?
The price and inventory of 93LC46AT-I/MC are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93LC46AT-I/MC is usually 5 days.
3.What payment methods are accepted for 93LC46AT-I/MC?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93LC46AT-I/MC transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93LC46AT-I/MC?
93LC46AT-I/MC orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93LC46AT-I/MC order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93LC46AT-I/MC?
For technical support, including 93LC46AT-I/MC datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93LC46AT-I/MC requirements.
6.How does Aetrix verify that 93LC46AT-I/MC is sourced from the original manufacturer or authorized distributors?
All 93LC46AT-I/MC products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93LC46AT-I/MC meets industry standards.
7.What is the process for return or replacement of 93LC46AT-I/MC?
All 93LC46AT-I/MC units undergo pre-shipment inspection (PSI). If there is an issue with 93LC46AT-I/MC, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93LC46AT-I/MC part is unused and in its original packaging.
Return procedure for 93LC46AT-I/MC:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
93LC46AT-I/MC Tags
-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology
-
AT21CS01-STUM10-T
Microchip Technology
-
AT24C02C-SSHM-T
Microchip Technology
-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics
-
AT24CS02-SSHM-T
Microchip Technology
-
93LC46BT-I/OT
Microchip Technology
-
AT24C04C-SSHM-T
Microchip Technology
-
24LC01BT-I/SN
Microchip Technology
-
24AA02UIDT-I/OT
Microchip Technology
-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
