Microchip Technology 93LC46C-E/ST

Overview

93LC46C-E/ST from Microchip Technology Inc. is a 1 Kbit low-voltage serial EEPROM with configurable 8-/16-bit word organization via the ORG pin, 2.5–5.5 V supply range, industrial and automotive temperature support (−40°C to +125°C), and Microwire-compatible 3-wire serial interface. It delivers 1 million erase/write cycles and >200 years data retention for nonvolatile parameter storage in embedded control systems.

For engineers reviewing the 93LC46C-E/ST datasheet, 93LC46C-E/ST pinout, 93LC46C-E/ST application, or 93LC46C-E/ST equivalent, key selection factors include ORG-pin-configurable memory width, Ready/Busy status signaling on DO, self-timed erase/write with auto-erase, power-on/off data protection, and compatibility with 3-wire serial microcontrollers in space-constrained designs.

Technical Context

The 93LC46C-E/ST implements a synchronous Microwire-compatible serial interface with CS, CLK, DI, and DO signals, where instruction execution begins on detection of a Start condition (CS high and DI high on CLK rising edge). Memory organization is dynamically selected by the logic level applied to the ORG pin: VSS enables 128 × 8-bit mode; VCC enables 64 × 16-bit mode.

It features hardware-based data protection including power-on reset detection (VCC ≥ 2.5 V required for operation), automatic entry into Erase/Write Disable (EWDS) state at power-up, and explicit EWEN/EWDS command control. All erase and write operations are self-timed, with ERAL and WRAL commands initiating full-array operations requiring VCC ≥ 4.5 V.

Key Specifications

Pinout & Package

93LC46C-E/ST is packaged in an 8-lead TSSOP (ST) with lead pitch 0.65 mm, body size 4.4 mm × 3.0 mm × 1.2 mm, Pb-free Matte Tin finish, and JEDEC-standard pinout. Pin 1 is marked by laser dot; package meets RoHS and JESD22-A110 reliability standards.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with 93LC46B-E/ST, the 93LC46C-E/ST offers runtime word-width reconfiguration; compared with AT25010B-SSHL-T, it reduces MCU GPIO usage by one pin and simplifies firmware for Microwire-native hosts, albeit at lower maximum clock rate.

Availability

93LC46C-E/ST is available at Aetrix Electronics and suitable for automotive control units, industrial programmable logic controllers, medical instrumentation, and consumer appliance firmware configuration requiring stable component supply across extended product lifecycles.

Supply support for 93LC46C-E/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontroller, analog, FPGA, and memory solutions, headquartered in Chandler, Arizona, serving automotive, industrial, communications, and consumer markets.

The 93LC46C-E/ST belongs to Microchip's legacy 93XX serial EEPROM family, designed specifically for low-power, pin-efficient nonvolatile storage in resource-constrained embedded systems requiring robust data integrity and broad temperature operation.

FAQ

What is the function of the ORG pin on the 93LC46C-E/ST?

The ORG pin on the 93LC46C-E/ST selects memory organization: logic high (VCC) configures 64 × 16-bit mode; logic low (VSS) configures 128 × 8-bit mode. This allows a single 93LC46C-E/ST part to interface with either 8-bit or 16-bit host systems. The pin must be externally biased - floating is not permitted - and its state is sampled at instruction start. No other 93LC46x variant supports this dynamic configuration; only the 'C' suffix models include ORG.

Does the 93LC46C-E/ST require external pull-up resistors on its I/O lines?

The 93LC46C-E/ST does not require external pull-ups on CS, CLK, or DI for basic operation, as internal weak pull-downs assist in idle-state stabilization. However, a 10 kΩ external pull-down on CS is recommended per Microchip application guidance to prevent spurious activation during power-up. DO is actively driven or High-Z - no pull-up needed unless shared with DI in bidirectional bus configurations, where a current-limiting resistor is mandatory to avoid bus conflict.

What is the minimum VCC required for the 93LC46C-E/ST to execute an ERAL or WRAL command?

The 93LC46C-E/ST requires VCC ≥ 4.5 V to reliably execute ERAL (Erase All) or WRAL (Write All) commands, as specified in DS20001749K-page 8 and page 11. Below this threshold, these commands may fail or produce undefined behavior. Standard READ, WRITE, and ERASE operations function across the full 2.5–5.5 V range, but full-array operations mandate the higher voltage to ensure complete oxide stress and charge injection across all memory cells.

How does the Ready/Busy status work on the DO pin of the 93LC46C-E/ST?

The DO pin of the 93LC46C-E/ST outputs Ready/Busy status during erase or write cycles: logic low indicates ongoing operation; logic high confirms completion. To read status, CS must be brought high for ≥250 ns after the initial instruction (TCSL), then sampled on subsequent CLK edges. DO returns to High-Z when CS goes low. Status polling avoids fixed timeouts and enables precise synchronization - critical for deterministic real-time systems using the 93LC46C-E/ST.

Is the 93LC46C-E/ST compatible with standard SPI interfaces?

The 93LC46C-E/ST is not SPI-compatible. It uses a Microwire-compatible 3-wire serial interface (CS, CLK, DI/DO) with distinct instruction encoding, timing, and protocol rules - e.g., Start condition detection, opcode formats for x8/x16 modes, and Ready/Busy signaling on DO. While some SPI masters can bit-bang Microwire timing, true SPI hardware peripherals (with MOSI/MISO/SCK/SS) cannot directly drive the 93LC46C-E/ST without firmware translation layer. Use only with Microwire-native or GPIO-bit-banged controllers.