Microchip Technology 93LC46XT/SN
- Part No.:
- 93LC46XT/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
93LC46XT/SN.pdf
- Description:
- IC EEPROM 1KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,566
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
93LC46XT/SN from Microchip Technology Inc. is a 1K-bit (128 × 8 or 64 × 16) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, ORG-pin-selectable memory organization, and industrial temperature range (–40°C to +85°C). It operates down to 2.5V, features self-timed erase/write cycles, and delivers 1 million endurance cycles with >200-year data retention - used in embedded system configuration storage, calibration data logging, and power-management parameter retention.
For engineers reviewing the 93LC46XT/SN datasheet, 93LC46XT/SN pinout, 93LC46XT/SN application, or 93LC46XT/SN equivalent, key selection considerations include its rotated SOIC (SN) package pinout, VCC range (2.5V–5.5V), standby current (3 µA at 2.5V), sequential read capability, and EWEN/EWDS write-protection protocol.
Technical Context
The 93LC46XT/SN implements a synchronous 3-wire Microwire interface with CS, CLK, DI, and DO lines, where instruction execution is triggered by a Start condition (CS high + DI high on first CLK rising edge). Memory organization (x8 or x16) is determined solely by the logic level on the ORG pin - tied to VCC for 64 × 16 mode, to VSS for 128 × 8 mode.
It uses self-timed internal programming logic: ERAL (Erase All) completes in 8 ms typical, WRAL (Write All) in 16 ms typical, and individual WRITE/ERASE operations in 4 ms per word. Ready/Busy status is actively signaled via DO pin during programming, requiring CS re-assertion after ≥250 ns low time (TCSL) to sample status.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 1 Kbit (128 × 8 or 64 × 16), selectable via ORG pin - enables flexible byte- or word-oriented data storage without external logic. |
| Supply voltage | 2.5V to 5.5V - supports direct interfacing with 3.3V and 5V microcontrollers; power-on protection activates below 1.4V. |
| Active read current | 100 µA typical at 2.5V - enables ultra-low-power operation in battery-backed or energy-harvesting systems. |
| Standby current | 3 µA typical at 2.5V - minimizes quiescent drain when CS is low and device is deselected. |
| Endurance | 1,000,000 erase/write cycles - ensures long-term reliability in firmware update or field-calibration applications. |
| Data retention | >200 years at 25°C - guarantees nonvolatile storage integrity across product lifecycle without refresh. |
| Interface | Industry-standard 3-wire Microwire (CS/CLK/DI/DO) - compatible with legacy MCU peripherals and requires only four GPIOs. |
Pinout & Package
8-pin rotated SOIC (SN) package per JEDEC MS-012, with pin 1 at bottom-left corner when notch faces up. Pin rotation distinguishes it from standard SOIC: CS at pin 3, CLK at pin 4, DI at pin 5, DO at pin 6, VSS at pin 7, ORG at pin 8, NU at pin 1, VCC at pin 2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| NU (Pin 1) | Not utilized | No internal connection; must be left unconnected or tied to VSS/VCC per layout best practice - no functional impact. |
| VCC (Pin 2) | Power supply | Accepts 2.5V–5.5V; internal power-on reset and voltage monitor ensure safe programming only above 1.4V. |
| CS (Pin 3) | Chip select | Active-high enable; falling edge initiates self-timed erase/write; must be held low ≥250 ns between instructions. |
| CLK (Pin 4) | Serial clock | Rising-edge synchronized I/O; clock can pause mid-transfer; no CLK required during auto-erase/write cycle. |
| DI (Pin 5) | Data input | Receives Start bit, opcode, address, and write data; supports shared bus with DO only at ≤1 MHz with x16 config. |
| DO (Pin 6) | Data output / Status | Outputs read data or RDY/BSY signal (low = busy); enters high-Z on CS falling edge; requires pull-up for status polling. |
| VSS (Pin 7) | Ground | Reference for all I/O and internal logic; must be low-impedance connection to minimize noise coupling. |
| ORG (Pin 8) | Memory organization | High = 64 × 16 (x16), low = 128 × 8 (x8); floating allowed only ≤1 MHz in x16 mode. |
Key Features
| Feature | Design Value |
|---|---|
| ORG-pin memory configuration | Hardware-selectable x8/x16 organization eliminates software overhead and enables single-BOM flexibility across byte- and word-addressed systems. |
| Self-timed erase/write | Internal timing eliminates need for external delay loops or watchdog coordination - simplifies firmware and improves deterministic response. |
| Power-on/off data protection | Automatic inhibition of programming below 1.4V prevents corruption during brown-out or hot-plug events without external supervisors. |
| Sequential read mode | Continuous data streaming across addresses while CS remains high - reduces transaction overhead for block reads (e.g., configuration tables). |
| EWEN/EWDS security protocol | Explicit enable/disable commands prevent accidental writes; device powers up in EWDS state - mandatory for robust field updates. |
Applications
| Industrial Sensor Calibration | Consumer Remote Control ID Storage |
|---|---|
Use Scenario: Storing factory-trimmed sensor offset/gain coefficients and temperature compensation tables in HVAC or process control transmitters. IC Role / Device Role / Timing Role: Nonvolatile configuration register accessed during power-up initialization and periodic recalibration routines. Use Value: Enables field-replaceable sensor modules with persistent calibration data independent of host MCU firmware version. | Use Scenario: Retaining unique IR code sets, button mapping profiles, and learning-mode history in universal remote controls. IC Role / Device Role / Timing Role: Low-power serial configuration store updated infrequently but read on every keypress or power cycle. Use Value: Supports multi-brand compatibility and user-customized layouts without increasing MCU flash usage or boot latency. |
| Medical Device Parameter Backup | Automotive Body Control Module Settings |
Use Scenario: Saving user-adjusted therapy parameters (e.g., infusion rate limits, alarm thresholds) in portable insulin pumps or nebulizers. IC Role / Device Role / Timing Role: Safety-critical data logger with guaranteed write completion signaling via DO pin status polling. Use Value: Meets IEC 62304 requirements for nonvolatile parameter persistence with verified write success before power removal. | Use Scenario: Storing seat/mirror position presets, lighting dimming curves, and door lock behavior in automotive BCMs. IC Role / Device Role / Timing Role: Configuration EEPROM interfaced directly to 8-bit MCU with limited peripheral resources. Use Value: Eliminates need for external SPI flash or larger MCU variants - reduces BOM cost and PCB area in cost-sensitive modules. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC46C-I/SN | Same 1K-bit capacity and rotated SOIC (SN) package, but revised silicon with improved ESD rating (≥4 kV HBM) and updated AC timing specs. | Recommended for new designs per Microchip notice; identical pinout and instruction set - drop-in replacement with enhanced robustness. | Select 93LC46C-I/SN for production releases requiring latest qualification and long-term availability. |
| AT93C46-10SU-2.7 | 1K-bit Microwire EEPROM in standard SOIC (not rotated); 2.7–5.5V VCC range; 1M endurance; same ORG-selectable x8/x16 organization. | Requires PCB layout change due to standard vs. rotated pinout; lacks explicit WRAL/ERAL support in datasheet - manual block erase needed. | Choose AT93C46-10SU-2.7 only if legacy board reuse mandates standard SOIC footprint and WRAL is not required. |
Compared with 93LC46XT/SN, the 93LC46C-I/SN offers identical functionality with higher ESD immunity and documented longevity, while the AT93C46-10SU-2.7 provides Microwire compatibility in standard SOIC but demands layout revision and lacks integrated bulk-programming commands.
Availability
93LC46XT/SN is available at Aetrix Electronics and suitable for industrial sensor calibration, medical device parameter backup, and automotive body control module settings requiring stable component supply and long-term obsolescence management.
Supply support for 93LC46XT/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, and Flash-IP solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 93LC series was designed specifically for low-voltage, low-pin-count serial EEPROM applications in space-constrained embedded systems - emphasizing micropower operation, hardware-configurable memory width, and robust data integrity under voltage transients.
FAQ
What is the difference between 93LC46XT/SN and 93LC46X-I/SN?
The 93LC46XT/SN is the tape-and-reel variant of the 93LC46X-I/SN - identical electrically and physically. The "T" suffix denotes packaging format for automated SMT placement; both share rotated SOIC (SN) pinout, –40°C to +85°C temperature grade, and 1K-bit Microwire EEPROM functionality. No performance or timing differences exist between them.
Does 93LC46XT/SN support true 3-wire SPI communication?
No - the 93LC46XT/SN implements Microwire protocol, not SPI. It uses separate DI and DO lines (4-wire physical interface) with strict Start-bit detection and opcode-based command framing. While functionally similar to SPI Mode 0, it lacks SPI's CPOL/CPHA configurability and requires precise Start condition timing, making direct SPI peripheral reuse nontrivial without firmware adaptation.
Can ORG pin be left floating on 93LC46XT/SN?
Only at clock frequencies ≤1 MHz and only when configured for x16 organization. For reliable operation at full speed (up to 2 MHz), ORG must be solidly tied to either VCC (for 64 × 16 mode) or VSS (for 128 × 8 mode). Floating ORG risks undefined memory mapping and read/write failures - Microchip explicitly recommends hard-wiring for production designs.
How is write completion verified on 93LC46XT/SN?
Write completion is verified by polling the DO pin: after initiating WRITE or WRAL, bring CS high for ≥250 ns, then sample DO - low indicates ongoing programming, high confirms completion. This Ready/Busy status replaces need for fixed delays; the 93LC46XT/SN does not support status register reads or interrupt outputs.
Is 93LC46XT/SN RoHS compliant?
Yes - the 93LC46XT/SN uses Pb-free matte tin (Sn) plating per JEDEC standards, as confirmed in Microchip's DS21712C packaging section. The "e3" marking on package denotes RoHS-compliant finish, and the SN package meets J-STD-609 Class 3 moisture sensitivity level (MSL-3) requirements.
93LC46XT/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 1Kbit
- Memory Organization:
- 128 x 8, 64 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
93LC46XT/SN FAQ
1.How can I place an order for 93LC46XT/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 93LC46XT/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93LC46XT/SN reliable?
The price and inventory of 93LC46XT/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93LC46XT/SN is usually 5 days.
3.What payment methods are accepted for 93LC46XT/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93LC46XT/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93LC46XT/SN?
93LC46XT/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93LC46XT/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93LC46XT/SN?
For technical support, including 93LC46XT/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93LC46XT/SN requirements.
6.How does Aetrix verify that 93LC46XT/SN is sourced from the original manufacturer or authorized distributors?
All 93LC46XT/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93LC46XT/SN meets industry standards.
7.What is the process for return or replacement of 93LC46XT/SN?
All 93LC46XT/SN units undergo pre-shipment inspection (PSI). If there is an issue with 93LC46XT/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93LC46XT/SN part is unused and in its original packaging.
Return procedure for 93LC46XT/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
93LC46XT/SN Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
