Microchip Technology 93LC66B-I/P
- Part No.:
- 93LC66B-I/P
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-DIP (0.300", 7.62mm)
- Datasheet:
-
93LC66B-I/P.pdf
- Description:
- IC EEPROM 4KBIT MICROWIRE 8DIP
- Quantity:
- Payment:

- Shipping:

Inventory:1,119
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
93LC66B-I/P from Microchip Technology Inc. is a 4 Kbit (256 × 16-bit) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, operating from 2.5 V to 5.5 V, rated for industrial temperature (−40°C to +85°C), and housed in an 8-lead PDIP package. It features self-timed erase/write cycles, automatic ERAL before WRAL, and Ready/Busy status signaling via DO pin - used in embedded system configuration storage and calibration data retention.
For engineers reviewing the 93LC66B-I/P datasheet, 93LC66B-I/P pinout, 93LC66B-I/P application, or 93LC66B-I/P equivalent, key selection considerations include its fixed 16-bit word organization (no ORG pin), 6 ms typical write cycle time, industrial-grade temperature support, and compatibility with legacy Microwire controllers requiring strict timing compliance per DS21795E.
Technical Context
The 93LC66B-I/P implements a synchronous serial interface using CS, CLK, and DI/DO signals with start-bit detection and opcode-driven command execution. Its memory array is organized as 256 words × 16 bits, with no ORG pin - eliminating external configuration logic required by 'C' variants.
It supports full instruction set including READ, WRITE, ERASE, ERAL, WRAL, EWEN, and EWDS, all executed via rising-edge clocked serial bitstreams. Status polling is enabled through DO pin behavior during programming, and power-on data protection ensures integrity during brown-out conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbit (256 × 16-bit) - provides compact nonvolatile storage for firmware parameters or device-specific settings without external address decoding. |
| VCC range | 2.5 V to 5.5 V - supports direct interfacing with 3.3 V and 5 V microcontrollers without level-shifting. |
| Write cycle time | 6 ms max (TWC) - defines minimum inter-write interval; impacts real-time logging latency and firmware update sequencing. |
| Endurance | 1,000,000 erase/write cycles - enables long-term field deployment in systems requiring frequent calibration updates. |
| Data retention | 200 years at 25°C - guarantees data integrity over product lifetime without refresh mechanisms. |
| Interface | Microwire-compatible 3-wire serial (CS/CLK/DI/DO) - requires only four GPIOs and matches legacy controller peripherals like PIC® MSSP modules. |
| Temperature grade | Industrial (−40°C to +85°C) - validated for use in industrial control panels, metering equipment, and automotive body electronics. |
Pinout & Package
8-lead PDIP (Plastic Dual In-line Package), 0.3 inch body width, through-hole mounting. Pin 1 marked by notch or dot; pin 1 ID confirmed by laser mark per DS21795E-page 18.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-high enable signal; must be held low ≥250 ns between instructions to reset internal state and avoid spurious commands. |
| CLK | Serial Clock | Rising-edge synchronized timing source; supports up to 3 MHz (VCC ≥4.5 V); clock may pause mid-transfer without corruption. |
| DI | Data Input | Serial input for start bit, opcodes, addresses, and write data; shares no internal path with DO - avoids bus contention when externally wired together. |
| DO | Data Output / Status | Tri-state output delivering read data or Ready/Busy status (low = busy); enters High-Z on CS falling edge. |
| VSS | Ground | Reference return for all I/O and core logic; must be connected before VCC during power-up to ensure POR stability. |
| NC | No Connection | Pin 7 has no internal bond; must remain unconnected - floating or tied to VSS/VCC risks undefined behavior per DS21795E-page 12. |
| VCC | Power Supply | Core supply input; voltage detect threshold is 1.5 V - below which all operations are inhibited to prevent partial writes. |
| ORG | Organization Select | Not present on 93LC66B - permanently configured for 16-bit word mode; pin 6 is NC and must not be driven. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed erase/write | Eliminates need for external timing control or watchdog timeout logic - simplifies host firmware and reduces CPU overhead during memory updates. |
| Automatic ERAL before WRAL | Ensures full-array readiness prior to bulk write, preventing partial overwrite failures and guaranteeing deterministic WRAL completion. |
| Ready/Busy status on DO | Enables efficient polling-based operation without dedicated interrupt lines - critical for resource-constrained MCUs lacking hardware SPI status flags. |
| Power-on/off data protection | Hardware-level lockout below 1.5 V VCC prevents corruption during power ramp-up/down - removes requirement for software write-protection sequences. |
| 1,000,000 endurance cycles | Supports daily calibration updates for >2,700 years at one write per day - exceeds typical industrial equipment service life requirements. |
Applications
| Industrial Sensor Calibration | Embedded System Configuration |
|---|---|
Use Scenario: Storing factory-trimmed gain/offset coefficients and linearization tables in pressure or temperature transmitters. IC Role / Device Role / Timing Role: Nonvolatile parameter store accessed during power-up and field recalibration; uses READ/WRITE with 6 ms write latency managed via status polling. Use Value: Enables field-serviceable calibration without firmware reflash; 200-year data retention ensures accuracy across multi-decade deployments. | Use Scenario: Holding user-configurable settings (e.g., display brightness, communication baud rate, alarm thresholds) in HVAC controllers. IC Role / Device Role / Timing Role: Serial configuration memory interfaced directly to MCU GPIOs; leverages Microwire protocol for minimal pin count and deterministic timing. Use Value: Reduces BOM cost vs. I²C EEPROMs by eliminating pull-up resistors; industrial temp rating ensures reliability in uncontrolled cabinet environments. |
| Automotive Body Control Module | Medical Device Usage Logs |
Use Scenario: Recording seat position memory, mirror presets, and lighting profiles in 12 V automotive systems with local 3.3 V regulation. IC Role / Device Role / Timing Role: Low-power EEPROM storing user preferences; operates within 2.5–5.5 V range compatible with post-regulator rails. Use Value: Meets AEC-Q100 stress test requirements for industrial temp grade; 1M endurance supports lifetime seat adjustment cycles. | Use Scenario: Logging usage timestamps, battery cycles, and error events in portable diagnostic instruments with infrequent but critical data writes. IC Role / Device Role / Timing Role: Tamper-resistant event logger using WRAL for atomic full-memory updates after session completion. Use Value: Automatic ERAL before WRAL guarantees log consistency even after unexpected power loss; 200-year retention satisfies medical audit trail mandates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC66B-I/SN | Same 256×16-bit organization and electrical specs, but in 8-lead SOIC package (surface-mount, 150 mil width). | Requires PCB redesign for SMT assembly; better thermal performance and smaller footprint than PDIP. | Select for automated manufacturing or space-constrained designs where through-hole is not required. |
| 93LC66A-I/P | Identical PDIP package and industrial rating, but 512×8-bit organization - double byte count, half word width. | Suitable for byte-oriented protocols (e.g., legacy 8-bit MCUs); incompatible with 16-bit address/data handling logic. | Choose only if host firmware expects 8-bit word access or memory map alignment differs. |
Compared with 93LC66B-I/SN, the 93LC66B-I/P offers through-hole reliability for prototyping and high-vibration environments; compared with 93LC66A-I/P, it delivers higher data density per access cycle but requires 16-bit data path support in the host controller.
Availability
93LC66B-I/P is available at Aetrix Electronics and suitable for industrial sensor calibration, embedded system configuration, and automotive body control modules requiring stable component supply across extended production lifecycles.
Supply support for 93LC66B-I/P includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, and Flash-IP solutions, headquartered in Chandler, Arizona, serving industrial, automotive, and consumer markets since 1989.
The 93LC66B belongs to Microchip's legacy 93XX serial EEPROM family, designed specifically for cost-sensitive, low-pin-count embedded systems needing reliable nonvolatile storage with Microwire compatibility and robust power-supply immunity.
FAQ
What is the memory organization of the 93LC66B-I/P?
The 93LC66B-I/P is a fixed 256 × 16-bit (4 Kbit) EEPROM with no ORG pin - it operates exclusively in 16-bit word mode. Unlike 'C' variants, it does not support runtime switching between 8-bit and 16-bit configurations. This simplifies hardware design by removing the need for external ORG logic, and ensures deterministic addressing behavior in all applications using the 93LC66B-I/P.
Does the 93LC66B-I/P require an external pull-up resistor on the DO line?
No, the 93LC66B-I/P does not require an external pull-up on DO. Its DO pin is actively driven high or low during READ or status polling, and enters High-Z when CS is low or during idle states. External pull-ups may cause contention or increased standby current. The 93LC66B-I/P datasheet specifies DO output drive strength per DC characteristics table D3/D4, confirming active push-pull capability without external biasing.
Can the 93LC66B-I/P be used with modern SPI controllers?
The 93LC66B-I/P is Microwire-compatible, not standard SPI - it uses a start-bit detection protocol and specific opcode framing that differs from SPI's continuous shift register model. While some SPI peripherals can emulate Microwire timing (e.g., certain PIC® MSSP modes), generic SPI master drivers will not function correctly with the 93LC66B-I/P without firmware-level protocol translation. Always verify controller support for Microwire mode before integration.
What is the purpose of the NC pin on the 93LC66B-I/P?
Pin 7 of the 93LC66B-I/P is designated NC (No Connection) - it has no internal bond wire or circuit connection. Per DS21795E-page 12, this pin must remain unconnected; tying it to VCC, VSS, or any signal risks undefined behavior or potential damage. The NC designation applies specifically to 'A' and 'B' variants like the 93LC66B-I/P; 'C' variants replace this pin with ORG functionality.
How does the 93LC66B-I/P handle power loss during a write cycle?
The 93LC66B-I/P incorporates hardware power-loss protection: its internal voltage detector disables all write operations when VCC falls below ~1.5 V (DS21795E-page 11). This prevents partial writes and data corruption. Additionally, the self-timed write architecture ensures that once initiated, the 6 ms erase/write cycle completes autonomously - no host intervention is needed. As long as VCC remains above threshold during the entire TWC window, the 93LC66B-I/P guarantees atomic update success.
93LC66B-I/P Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 256 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 6ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 8-PDIP
93LC66B-I/P FAQ
1.How can I place an order for 93LC66B-I/P through Aetrix?
Please submit a Request for Quotation (RFQ) for 93LC66B-I/P on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93LC66B-I/P reliable?
The price and inventory of 93LC66B-I/P are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93LC66B-I/P is usually 5 days.
3.What payment methods are accepted for 93LC66B-I/P?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93LC66B-I/P transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93LC66B-I/P?
93LC66B-I/P orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93LC66B-I/P order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93LC66B-I/P?
For technical support, including 93LC66B-I/P datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93LC66B-I/P requirements.
6.How does Aetrix verify that 93LC66B-I/P is sourced from the original manufacturer or authorized distributors?
All 93LC66B-I/P products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93LC66B-I/P meets industry standards.
7.What is the process for return or replacement of 93LC66B-I/P?
All 93LC66B-I/P units undergo pre-shipment inspection (PSI). If there is an issue with 93LC66B-I/P, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93LC66B-I/P part is unused and in its original packaging.
Return procedure for 93LC66B-I/P:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
93LC66B-I/P Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

