Microchip Technology 93LC66BT-E/SN
- Part No.:
- 93LC66BT-E/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
93LC66BT-E/SN.pdf
- Description:
- IC EEPROM 4KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,616
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
93LC66BT-E/SN from Microchip Technology Inc. is a 4 Kbit low-voltage serial EEPROM with 512 × 8-bit organization, Microwire-compatible 3-wire interface (CS/CLK/DI/DO), and automotive-grade temperature range (−40°C to +125°C). It features self-timed erase/write cycles, automatic ERAL before WRAL, power-on/off data protection, and 1,000,000 endurance cycles - used in engine control units for calibration storage.
For engineers reviewing the 93LC66BT-E/SN datasheet, 93LC66BT-E/SN pinout, 93LC66BT-E/SN application, or 93LC66BT-E/SN equivalent, key selection criteria include VCC range (2.5–5.5 V), automotive temp rating, SOIC-8 package compatibility, and Microwire protocol timing compliance at 2 MHz (VCC = 2.5 V).
Technical Context
The 93LC66BT-E/SN implements a synchronous serial Microwire interface with dedicated CS, CLK, DI, and DO pins; no ORG pin (fixed 8-bit word size). It uses internal auto-erase prior to write and supports sequential read, ERAL, WRAL, EWEN/EWDS commands for robust nonvolatile memory management.
Its Ready/Busy status is signaled via DO pin during erase/write operations, requiring CS high ≥250 ns after TCSL to sample. Power-on reset logic disables programming until explicit EWEN command is issued, ensuring data integrity during brown-out conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbit (512 × 8-bit) - fixed x8 organization, no ORG pin |
| VCC range | 2.5 V to 5.5 V - supports wide supply rails including 3.3 V and 5 V systems |
| Temp range | −40°C to +125°C (Automotive E grade) - qualified for under-hood applications |
| Write cycle time | 6 ms max (TWC) - self-timed; no external delay required in firmware |
| Endurance | 1,000,000 erase/write cycles - ensures long-term reliability in field-updatable systems |
| Data retention | >200 years - maintains calibration data across product lifetime without refresh |
| Interface | Microwire 3-wire serial (CS/CLK/DI/DO) - minimal GPIO usage, compatible with legacy MCU peripherals |
Pinout & Package
Package: 8-lead SOIC (SN), Pb-free Matte Tin finish, body size 3.9 mm × 4.9 mm, standard JEDEC MS-012AA footprint.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 CS | Chip Select | Active-high enable; must be held ≥250 ns low between instructions; initiates self-timed write on falling edge |
| 2 CLK | Serial Clock | Positive-edge synchronized I/O; clocking stops freely during transmission; no clock required during write cycle |
| 3 DI | Data Input | Accepts Start bit, opcode, address, and data; tied to DO via resistor if shared bus to prevent conflict |
| 4 DO | Data Output / Status | Outputs read data or Ready/Busy (low = busy); enters High-Z on CS falling edge |
| 5 VSS | Ground | Reference return path; decoupling capacitor required within 10 mm of pin |
| 6 NC | No Connection | Internally unconnected; must be left floating or tied to VSS per layout best practice |
| 7 NC | No Connection | Internally unconnected; not bonded; avoid routing signals nearby |
| 8 VCC | Power Supply | 2.5–5.5 V input; POR threshold at 1.5 V; voltage detect prevents writes below safe level |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed erase/write | Eliminates need for external timing loops or watchdog timeouts in host firmware |
| Auto-ERAL before WRAL | Guarantees full-array erase before bulk write, preventing partial-data corruption |
| Power-on/off data protection | Hardware-level lockout below 1.5 V VCC prevents inadvertent writes during power ramp |
| Ready/Busy polling via DO | Enables non-blocking host operation - CPU can service other tasks while EEPROM busy |
| EWEN/EWDS security | Explicit enable/disable sequence prevents accidental overwrites; device powers up in EWDS state |
Applications
| Engine Control Unit (ECU) | Industrial PLC Configuration |
|---|---|
Use Scenario: Storing fuel map calibration tables and fault codes in automotive powertrain systems. IC Role / Device Role / Timing Role: Nonvolatile parameter storage with AEC-Q100-aligned reliability and −40°C to +125°C operation. Use Value: Enables field updates without hardware change; 200-year data retention preserves calibration across vehicle lifetime. | Use Scenario: Retaining I/O mapping, PID tuning parameters, and user-defined logic states after power loss. IC Role / Device Role / Timing Role: Serial configuration memory interfaced to ARM Cortex-M or PIC MCU via GPIO bit-banged Microwire. Use Value: Reduces BOM count vs parallel EEPROM; SOIC-8 fits compact industrial PCB layouts. |
| Medical Infusion Pump | Smart Meter Firmware Patch Storage |
Use Scenario: Holding dosage history, alarm thresholds, and regulatory audit logs requiring tamper-resistant storage. IC Role / Device Role / Timing Role: Secure, low-power EEPROM with write-protection logic (EWEN/EWDS) and 1M-cycle endurance. Use Value: Meets IEC 62304 software lifecycle requirements; no external write-enable signal needed. | Use Scenario: Storing encrypted firmware patches and cryptographic keys for OTA updates in utility meters. IC Role / Device Role / Timing Role: Trusted nonvolatile memory with deterministic 6 ms write latency and VCC brown-out immunity. Use Value: Ensures atomic patch writes - power failure during update leaves memory in known-good state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC66B-I/SN | Industrial grade (−40°C to +85°C); same 512×8-bit, SOIC-8, 2.5–5.5 V | Lacks automotive qualification; unsuitable for under-hood or safety-critical use | Select only for cost-sensitive commercial applications where extended temperature is not required |
| AT25DF041A-SH-B | SPI interface (4-wire), 4 Mbit density, 2.7–3.6 V only, no EWEN/EWDS command set | Higher density but incompatible protocol; requires SPI peripheral and different driver stack | Choose only when migrating to SPI-based architecture and needing >4 Kbit capacity |
Compared with 93LC66B-I/SN, the 93LC66BT-E/SN adds automotive qualification and tighter VCC min spec (2.5 V vs 2.5 V), while AT25DF041A-SH-B trades Microwire simplicity for SPI bandwidth and density - neither offers drop-in replacement capability.
Availability
93LC66BT-E/SN is available at Aetrix Electronics and suitable for automotive control modules, industrial programmable logic controllers, and medical device data logging requiring stable component supply and long-term lifecycle support.
Supply support for 93LC66BT-E/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog components, and memory solutions, headquartered in Chandler, Arizona.
The 93LC66BT-E/SN belongs to Microchip's legacy 93XX serial EEPROM family, designed specifically for cost-sensitive, low-pin-count embedded systems requiring reliable nonvolatile storage with minimal MCU resource usage.
FAQ
What is the maximum clock frequency supported by the 93LC66BT-E/SN?
The 93LC66BT-E/SN supports up to 2 MHz clock frequency when VCC = 2.5 V, and up to 3 MHz when VCC ≥ 4.5 V. This is specified in Table 1-2 (AC Characteristics) of DS21795E. The actual usable frequency depends on board-level signal integrity and load capacitance - keep CLK trace short and routed away from noise sources to maintain timing margins for the 93LC66BT-E/SN.
Does the 93LC66BT-E/SN have an ORG pin?
No, the 93LC66BT-E/SN does not have an ORG pin. As a 'B'-suffix variant in the 93LC66x series, it is a fixed 16-bit organization device - but the 'T' suffix in 93LC66BT indicates it is the 8-bit version ('A' type). Per Device Selection Table, 93LC66A has no ORG pin and is 512 × 8-bit. Therefore, 93LC66BT-E/SN is 8-bit only, with pins 6 and 7 marked NC (no connection), confirming absence of ORG functionality in the 93LC66BT-E/SN.
How is write protection implemented on the 93LC66BT-E/SN?
Write protection on the 93LC66BT-E/SN is implemented via EWEN (Erase/Write Enable) and EWDS (Erase/Write Disable) commands. The device powers up in EWDS mode, blocking all erase/write operations until EWEN is issued. After any write, best practice is to issue EWDS to re-lock. This two-command scheme provides firmware-level control without external hardware pins, making the 93LC66BT-E/SN resistant to accidental overwrites during power transients or software faults.
What package type does the 93LC66BT-E/SN use?
The 93LC66BT-E/SN uses an 8-lead SOIC package (package code SN), with standard JEDEC MS-012AA dimensions (3.9 mm × 4.9 mm body, 1.27 mm lead pitch). It features Pb-free Matte Tin (Sn) finish and is RoHS compliant. Pin 1 is marked by a laser dot or notch; the exposed pad is absent - this distinguishes it from DFN/TDFN variants like MN/MC. The SOIC-8 footprint ensures direct compatibility with legacy 93LC66A/B/C designs using the 93LC66BT-E/SN.
Can the 93LC66BT-E/SN be used in a shared bus configuration with DI and DO connected?
Yes, the 93LC66BT-E/SN supports shared bus (DI/DO tied together) but requires a current-limiting resistor (typically 1–10 kΩ) between them to prevent bus conflict during the dummy zero preceding read operations. Without the resistor, undefined voltage levels may occur if address bit A0 is high, risking data corruption. This configuration reduces pin count on resource-constrained MCUs but adds one passive component - verified in Section 2.2 of DS21795E for the 93LC66BT-E/SN.
93LC66BT-E/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 256 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 6ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
93LC66BT-E/SN FAQ
1.How can I place an order for 93LC66BT-E/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 93LC66BT-E/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93LC66BT-E/SN reliable?
The price and inventory of 93LC66BT-E/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93LC66BT-E/SN is usually 5 days.
3.What payment methods are accepted for 93LC66BT-E/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93LC66BT-E/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93LC66BT-E/SN?
93LC66BT-E/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93LC66BT-E/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93LC66BT-E/SN?
For technical support, including 93LC66BT-E/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93LC66BT-E/SN requirements.
6.How does Aetrix verify that 93LC66BT-E/SN is sourced from the original manufacturer or authorized distributors?
All 93LC66BT-E/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93LC66BT-E/SN meets industry standards.
7.What is the process for return or replacement of 93LC66BT-E/SN?
All 93LC66BT-E/SN units undergo pre-shipment inspection (PSI). If there is an issue with 93LC66BT-E/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93LC66BT-E/SN part is unused and in its original packaging.
Return procedure for 93LC66BT-E/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
93LC66BT-E/SN Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
