Microchip Technology 93LC66C-E/ST

Overview

93LC66C-E/ST from Microchip Technology Inc. is a 4 Kbit low-voltage serial EEPROM with configurable 8-/16-bit word organization via the ORG pin, 2.5–5.5 V supply range, industrial and automotive temperature support (−40°C to +125°C), and Microwire-compatible 3-wire serial interface. It delivers 1 million erase/write cycles and >200 years data retention for nonvolatile storage in microcontroller-based systems.

For engineers reviewing the 93LC66C-E/ST datasheet, 93LC66C-E/ST pinout, 93LC66C-E/ST application, or 93LC66C-E/ST equivalent, key selection criteria include ORG-pin-configurable memory width, Ready/Busy status signaling on DO, self-timed erase/write with auto-erase, power-on/off data protection, and compatibility with legacy Microwire controllers in space-constrained embedded designs.

Technical Context

The 93LC66C-E/ST implements a synchronous 3-wire Microwire interface with CS, CLK, and DI/DO lines, where instruction execution begins on detection of a Start bit (CS high and DI high on CLK rising edge). Memory organization is dynamically selected: ORG = VSS enables 512 × 8-bit mode; ORG = VCC enables 256 × 16-bit mode.

It features hardware-level data protection including power-on reset detection (V_POR = 2.5 V typ.), EWEN/EWDS command lockout, and automatic ERAL before WRAL. Programming cycles are fully self-timed - falling edge of CS initiates erase/write for 93LC versions, with DO asserting Ready/Busy status when CS is reasserted after ≥250 ns low time.

Key Specifications

Pinout & Package

93LC66C-E/ST is packaged in an 8-lead TSSOP (ST) with exposed pad option per Microchip DS21795E. Pin 1 is marked by laser dot; package dimensions comply with JEDEC MO-153AA.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with 93LC66B-E/ST, the 93LC66C-E/ST adds ORG-driven configurability at identical package and temperature specs; versus AT25DF041A-SSH-T, it offers broader V_CC range and Microwire simplicity but lower density and slower write speed - making it optimal for resource-constrained, voltage-flexible, legacy-interface designs.

Availability

93LC66C-E/ST is available at Aetrix Electronics and suitable for industrial sensor calibration, automotive body control modules, medical device configuration, and consumer appliance settings storage requiring stable component supply across extended product lifecycles.

Supply support for 93LC66C-E/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.

The 93LC66C-E/ST belongs to Microchip's legacy 93XX serial EEPROM family, designed specifically for low-power, pin-efficient nonvolatile storage in cost-sensitive and space-constrained embedded systems using Microwire-compatible controllers.

FAQ

What is the function of the ORG pin on the 93LC66C-E/ST?

The ORG pin on the 93LC66C-E/ST selects memory organization: tied to VCC it configures the device as 256 × 16-bit; tied to VSS it configures as 512 × 8-bit. This dual-mode capability allows one 93LC66C-E/ST design to serve both 8-bit and 16-bit host systems. The pin must be statically biased - floating or dynamic control is not supported. This feature is exclusive to 'C' variants; 'A' and 'B' versions lack ORG and are fixed-width.

Does the 93LC66C-E/ST support SPI communication?

No, the 93LC66C-E/ST does not support SPI. It implements a Microwire-compatible 3-wire serial interface (CS, CLK, DI/DO) with specific instruction encoding and timing per Microchip DS21795E. While electrically similar to SPI's 3-wire mode, its opcode set, start condition detection (CS and DI high on CLK rise), and status reporting (DO as Ready/Busy) are incompatible with standard SPI controllers without firmware adaptation.

What is the maximum clock frequency supported by the 93LC66C-E/ST at 3.3 V?

At V_CC = 3.3 V (within 2.5–5.5 V range), the 93LC66C-E/ST supports a maximum clock frequency of 2 MHz per Table 1-2 (A1). This is confirmed for 2.5 V ≤ V_CC < 5.5 V operation. Timing parameters including T_CKH (200 ns min), T_CKL (200 ns min), and T_PD (250 ns max) are specified under these conditions, ensuring reliable communication with common 3.3 V microcontrollers.

How does the 93LC66C-E/ST protect against accidental writes during power-up?

The 93LC66C-E/ST incorporates hardware power-on reset (POR) detection that inhibits all write operations until V_CC exceeds ~2.5 V. Additionally, it powers up in Erase/Write Disable (EWDS) mode - requiring an explicit EWEN command before any ERASE or WRITE instruction executes. These dual protections prevent spurious writes during brown-out, hot-plug, or unstable power ramp-up, ensuring data integrity without external supervision circuitry.

Can the 93LC66C-E/ST be used in a single-line (DI/DO shared) configuration?

Yes, the 93LC66C-E/ST supports single-line bus configuration where DI and DO are connected together, but a series resistor (typically 100–1 kΩ) is required between the MCU I/O pin and the device to prevent bus conflict during the dummy zero preceding READ. This conflict arises if address bit A0 is high, causing undefined voltage at DO. The resistor limits current and stabilizes the line, enabling bidirectional communication on one trace - useful for pin-constrained designs.