Microchip Technology 93LC66/SN
- Part No.:
- 93LC66/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
93LC66/SN.pdf
- Description:
- IC EEPROM 4KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:3,552
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
93LC66/SN from Microchip Technology Inc. is a 4 Kbit (512 × 8 or 256 × 16) low-voltage serial EEPROM with Microwire™ interface, ORG-pin-selectable memory organization, and industrial temperature range (–40°C to +85°C). It operates down to 2.5 V, features self-timed erase/write cycles, 1 million endurance cycles, and >200-year data retention. Used for configuration storage in embedded controllers and power management systems.
For engineers reviewing the 93LC66/SN datasheet, 93LC66/SN pinout, 93LC66/SN application, or 93LC66/SN equivalent, key selection criteria include its 3-wire serial interface timing (max 2 MHz at VCC < 4.5 V), dual x8/x16 organization flexibility, power-on/off data protection, and SOIC-8 (SN) package compatibility with legacy board layouts.
Technical Context
The 93LC66/SN implements a synchronous 3-wire Microwire-compatible interface with CS, CLK, and bidirectional DI/DO lines. Its internal logic decodes 10-bit addresses (x8 mode) or 8-bit addresses (x16 mode) based on ORG pin state, supporting READ, WRITE, ERASE, ERAL, WRAL, EWEN, and EWDS instructions with clocked opcode/address/data sequences.
It uses CMOS nonvolatile floating-gate technology with automatic pre-erase (ERAL before WRAL), device status signaling via DO pin during programming, and power-supply monitoring circuitry that inhibits write operations below 1.4 V. All erase/write cycles are fully self-timed and require no external timing control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 4 Kbit (512 × 8 or 256 × 16 bits), selectable via ORG pin - enables flexible byte- or word-oriented firmware storage |
| Supply voltage | 2.5 V to 5.5 V - supports direct interfacing with 2.5 V, 3.3 V, and 5 V microcontrollers without level shifters |
| Interface | 3-wire Microwire™ serial (CS, CLK, DI/DO) - minimal GPIO usage; compatible with legacy PIC® and 8051-based designs |
| Write endurance | 1,000,000 erase/write cycles - ensures long-term reliability in frequent configuration update applications |
| Data retention | >200 years at 25°C - suitable for unattended industrial equipment requiring decades of nonvolatile storage integrity |
| Operating temperature | –40°C to +85°C (Industrial grade) - validated for use in automotive body control modules and industrial PLC I/O cards |
| Max clock frequency | 2 MHz at VCC < 4.5 V - defines maximum instruction throughput; limits burst read/write speed in low-voltage operation |
Pinout & Package
8-pin SOIC (SN) package per JEDEC MS-012, 150-mil width, surface-mount compatible. Pin 1 marked by notch or dot; pin 1 is CS.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS (Pin 1) | Chip Select | Active-high enable; must be held low ≥250 ns between instructions; initiates self-timed programming on falling edge |
| CLK (Pin 2) | Serial Clock | Synchronizes all data transfers; rising-edge sampling of DI and DO; stoppable mid-sequence without corruption |
| DI (Pin 3) | Data Input | Receives Start bit, opcode, address, and write data; shares net with DO only if bus conflict mitigation is implemented |
| DO (Pin 4) | Data Output / Status | Outputs read data or Ready/Busy status (low = busy); high-Z when inactive; requires pull-up for reliable status polling |
| VSS (Pin 5) | Ground | Reference return path for all digital and analog functions; must be low-impedance connection to system GND plane |
| ORG (Pin 6) | Organization Select | Tied to VCC for x16 mode (256 words), VSS for x8 mode (512 bytes); floating allowed only ≤1 MHz in x16 mode |
| NU (Pin 7) | No Connect | Internally unconnected; must be left floating or tied to VSS/VCC per PCB layout best practices - no functional role |
| VCC (Pin 8) | Power Supply | 2.5–5.5 V supply; includes internal voltage monitor that blocks writes below 1.4 V during power-up/down transitions |
Key Features
| Feature | Design Value |
|---|---|
| ORG-pin memory configuration | Hardware-selectable x8 or x16 organization eliminates need for software rework when migrating between byte- and word-addressed firmware layouts |
| Self-timed erase/write | Eliminates external timing components and host CPU wait-state management - WRAL completes in 16 ms typical, independent of clock rate |
| Power-on/off data protection | Hardware-enforced write inhibition below 1.4 V prevents corruption during brown-out or cold-start conditions without firmware intervention |
| Sequential read mode | Enables continuous block reads with single CS assertion - reduces transaction overhead for loading multi-byte calibration tables |
| Status polling via DO | Allows real-time readiness verification during programming without dedicated status registers or interrupts - simplifies driver implementation |
Applications
| Industrial Sensor Calibration | Embedded Controller Configuration |
|---|---|
|
Use Scenario: Storing factory-trimmed sensor offset/gain coefficients and linearization tables in environmental monitoring nodes. IC Role / Device Role / Timing Role: Nonvolatile configuration storage with infrequent updates and guaranteed data integrity over 10+ years of field operation. Use Value: Eliminates need for external backup batteries or supercapacitors; >200-year retention ensures calibration persistence across product lifecycle. |
Use Scenario: Holding boot-time configuration parameters (baud rate, I/O mapping, watchdog timeout) for microcontroller-based motor drives. IC Role / Device Role / Timing Role: Serial parameter store accessed during early boot sequence via simple GPIO bit-banging or hardware SPI/Microwire peripheral. Use Value: Reduces BOM count versus parallel EEPROM; 2.5 V operation allows direct interface with low-power MCUs without level translation. |
| Power Management Unit Settings | Legacy Industrial PLC I/O Modules |
|
Use Scenario: Saving user-defined voltage/current thresholds and fault response modes in AC/DC power supplies with digital control. IC Role / Device Role / Timing Role: Secure, low-pin-count NVM for safety-critical settings updated only during maintenance mode. Use Value: Built-in EWEN/EWDS commands prevent accidental writes; 1M endurance supports thousands of commissioning cycles over product life. |
Use Scenario: Retaining module identification, channel calibration, and diagnostic history in DIN-rail mounted I/O expansion units. IC Role / Device Role / Timing Role: Drop-in replacement for obsolete 93LC66-I/P in existing SOIC footprints; same pinout and instruction set as legacy designs. Use Value: SN package matches standard 150-mil SOIC land patterns; industrial temp rating ensures reliability in unventilated control cabinets. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC66C-I/SN | Enhanced version with improved ESD rating (≥4 kV HBM), tighter tPD spec (400 ns max), and extended VCC range (1.8–5.5 V) | Required for new designs targeting IEC 61000-4-2 compliance or 1.8 V host interfaces | Select 93LC66C-I/SN for new designs; 93LC66/SN remains valid for legacy repair and continuity builds |
| AT25040B-MAU-1.8 | 4 Kbit SPI interface (4-wire), 1.8–5.5 V operation, 20 MHz max clock, 100-year retention, no ORG pin - fixed 512 × 8 organization | Used where higher-speed SPI is available and x16 mode is unnecessary; lacks hardware organization select | Choose AT25040B-MAU-1.8 only if migrating to SPI infrastructure and accepting loss of x16 flexibility |
Compared with 93LC66C-I/SN, the 93LC66/SN offers identical pinout and instruction set but lacks 1.8 V support and enhanced ESD robustness; compared with AT25040B-MAU-1.8, it provides ORG-selectable organization and Microwire compatibility but lower maximum clock speed and no SPI-native interface.
Availability
93LC66/SN is available at Aetrix Electronics and suitable for industrial sensor calibration, embedded controller configuration, and power management unit settings requiring stable component supply and long-term obsolescence management.
Supply support for 93LC66/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.
The 93LC66/SN belongs to Microchip's legacy 93LC serial EEPROM family, designed specifically for cost-sensitive, low-pin-count nonvolatile storage in industrial and automotive subsystems where Microwire interface compatibility and long data retention are critical.
FAQ
What is the memory organization of 93LC66/SN and how is it selected?
The 93LC66/SN supports two memory organizations: 512 × 8 bits (x8) or 256 × 16 bits (x16), selected by the logic level applied to the ORG pin. When ORG is tied to VSS, x8 mode is active; when tied to VCC, x16 mode is active. The 93LC66/SN datasheet specifies that ORG may be floated only at clock frequencies ≤1 MHz in x16 mode. This hardware-selectable configuration allows one device to serve multiple firmware architectures without redesign.
Does 93LC66/SN support true SPI communication?
No, the 93LC66/SN implements a 3-wire Microwire™ interface (CS, CLK, DI/DO), not standard 4-wire SPI. It lacks separate SI/SO lines and uses a shared bidirectional data line with start-bit detection. While functionally similar for basic read/write, it does not support SPI mode settings (CPOL/CPHA) or daisy-chaining. The 93LC66/SN requires host-side bit-banging or Microwire-compatible peripheral support - not generic SPI hardware.
What is the purpose of the NU pin on 93LC66/SN?
Pin 7 of the 93LC66/SN is labeled NU (No Connect) in the official pin function table and is internally unconnected. It must be left floating on the PCB; tying it to VCC or VSS has no functional effect but may improve mechanical stability or reduce noise coupling in high-density layouts. The 93LC66/SN datasheet explicitly states NU has no electrical role and should not be used as a ground or supply tie point.
How does the 93LC66/SN indicate readiness after a write operation?
The 93LC66/SN signals readiness via the DO pin: during an erase or write cycle, DO outputs a low (busy) signal until completion, then transitions high (ready). To poll status, CS must be brought high for ≥250 ns after the initial CS low pulse, and DO must be read while CS is high. A pull-up resistor is required on DO to ensure valid high-level detection. This mechanism applies identically across all 93LC66/SN programming operations including WRAL and ERAL.
Is 93LC66/SN suitable for new designs?
No - Microchip explicitly marks the 93LC66/SN as "Not recommended for new designs" in the datasheet, advising migration to the enhanced 93LC66C-I/SN variant. The 93LC66/SN remains fully supported for legacy repair, continuity builds, and obsolescence management, but new projects should use 93LC66C-I/SN for improved 1.8 V operation, higher ESD immunity, and extended qualification. Aetrix Electronics maintains inventory of 93LC66/SN specifically for these legacy-support scenarios.
93LC66/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 4Kbit
- Memory Organization:
- 512 x 8, 256 x 16
- Memory Interface:
- Microwire
- Clock Frequency:
- 2 MHz
- Write Cycle Time - Word, Page:
- 10ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
93LC66/SN FAQ
1.How can I place an order for 93LC66/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 93LC66/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93LC66/SN reliable?
The price and inventory of 93LC66/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93LC66/SN is usually 5 days.
3.What payment methods are accepted for 93LC66/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93LC66/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93LC66/SN?
93LC66/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93LC66/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93LC66/SN?
For technical support, including 93LC66/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93LC66/SN requirements.
6.How does Aetrix verify that 93LC66/SN is sourced from the original manufacturer or authorized distributors?
All 93LC66/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93LC66/SN meets industry standards.
7.What is the process for return or replacement of 93LC66/SN?
All 93LC66/SN units undergo pre-shipment inspection (PSI). If there is an issue with 93LC66/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93LC66/SN part is unused and in its original packaging.
Return procedure for 93LC66/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
93LC66/SN Tags

-
M24C02-WMN6TP
STMicroelectronics
-
AT24C02C-XHM-T
Microchip Technology

-
AT21CS01-STUM10-T
Microchip Technology

-
AT24C02C-SSHM-T
Microchip Technology

-
24LC01BT-I/OT
Microchip Technology
-
M24C02-FMC6TG
STMicroelectronics

-
AT24CS02-SSHM-T
Microchip Technology

-
93LC46BT-I/OT
Microchip Technology

-
AT24C04C-SSHM-T
Microchip Technology

-
24LC01BT-I/SN
Microchip Technology

-
24AA02UIDT-I/OT
Microchip Technology

-
AT24C08C-STUM-T
Microchip Technology
Tech Hub
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
