Microchip Technology 93LC86A-I/SN
- Part No.:
- 93LC86A-I/SN
- Manufacturer:
- Microchip Technology
- Category:
- Memory
- Package:
- 8-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
93LC86A-I/SN.pdf
- Description:
- IC EEPROM 16KBIT MICROWIRE 8SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:792
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Product details
Overview
93LC86A-I/SN from Microchip Technology Inc. is a 16 Kbit (2048 × 8-bit) low-voltage serial EEPROM with Microwire-compatible 3-wire interface, operating from 2.5V to 5.5V, rated for -40°C to +85°C industrial temperature range, and housed in an 8-lead SOIC (SN) package. It delivers nonvolatile storage for configuration data in embedded controllers, power management ICs, and sensor calibration modules.
For engineers reviewing the 93LC86A-I/SN datasheet, 93LC86A-I/SN pinout, 93LC86A-I/SN application, or 93LC86A-I/SN equivalent, key selection criteria include its 8-bit fixed organization, self-timed 5 ms write cycle, Ready/Busy status via DO pin, 1 million erase/write endurance, and compatibility with legacy Microwire host controllers requiring CS/CLK/DI/DO signaling.
Technical Context
The 93LC86A-I/SN implements a synchronous serial Microwire protocol with dedicated CS, CLK, DI, and DO pins-no ORG or PE pins (unlike 'C' variants). All instructions (READ, WRITE, ERASE, ERAL, WRAL, EWEN, EWDS) are initiated by a Start bit followed by opcode, address, and data bits clocked on CLK rising edges.
It features automatic erase-before-write, sequential read capability, and power-on/off data protection. The DO pin serves dual function: serial data output during READ and Ready/Busy status indicator during programming-low = busy, high = ready-after CS reassertion following minimum TCSL (250 ns).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Memory size | 16 Kbit (2048 × 8-bit), fixed x8 organization-no ORG pin required or present. |
| VCC range | 2.5V to 5.5V-supports wide supply rails including 3.3V and 5V systems without level shifting. |
| Write cycle time | 5 ms max (TWC)-self-timed; no external timing control needed for erase/write completion. |
| Endurance | 1,000,000 erase/write cycles-ensures long-term reliability in field-updatable applications. |
| Data retention | 200 years at 25°C-guarantees persistent storage across product lifecycles. |
| Interface | Microwire-compatible 3-wire serial (CS/CLK/DI/DO)-direct drop-in replacement for legacy Microwire EEPROMs. |
| Temp range | -40°C to +85°C (Industrial grade)-validated for operation in industrial control and automotive cabin environments. |
Pinout & Package
8-lead SOIC (SN) package per Microchip drawing C04-037, 3.9 mm × 4.9 mm body, 1.27 mm pitch, Pb-free Matte Tin finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CS | Chip Select | Active-high enable; device enters Standby mode when low; must be held low ≥250 ns between instructions. |
| CLK | Serial Clock | Synchronizes all data transfers; opcodes, addresses, and data clocked in/out on rising edge. |
| DI | Data Input | Receives Start bit, instruction opcodes, addresses, and write data; no internal pull-up/down. |
| DO | Data Output / Status | Outputs read data or Ready/Busy status (low = busy); tri-stated when CS low or during non-read operations. |
| VSS | Ground | Reference return path for all digital and analog functions; must be connected to system ground plane. |
| VCC | Power Supply | Primary supply input; internal voltage detector (VPOR = 1.5V typ.) prevents writes below safe threshold. |
Key Features
| Feature | Design Value |
|---|---|
| Self-timed Erase/Write | Eliminates need for external timing circuitry or software delays-device asserts Ready/Busy on DO automatically. |
| Power-On/Off Data Protection | Hardware-level VCC monitoring prevents inadvertent writes during brown-out or power ramp-up/down sequences. |
| Sequential Read Function | Enables burst reads across consecutive addresses with single CS assertion-reduces host overhead and bus traffic. |
| Industry Standard 3-Wire Serial I/O | Ensures interoperability with existing Microwire-based microcontrollers and FPGAs without protocol translation. |
| Ready/Busy Status Signal | Allows polling-based programming flow control-host avoids blind waits and optimizes interrupt latency. |
Applications
| Motor Control Configuration | Smart Sensor Calibration |
|---|---|
Use Scenario: Storing motor phase timing offsets, current limit thresholds, and PID coefficients in BLDC driver modules. IC Role / Device Role / Timing Role: Nonvolatile parameter storage accessed at boot and updated during field calibration routines. Use Value: Enables factory and field recalibration without firmware reflashing; retains settings across 10+ years of operation. | Use Scenario: Holding temperature-compensated offset/gain coefficients for MEMS accelerometers and pressure transducers. IC Role / Device Role / Timing Role: Persistent memory for sensor linearization data loaded at power-on by host MCU. Use Value: Achieves ±0.1% full-scale accuracy over -40°C to +85°C without external reference storage. |
| Power Management IC Settings | Industrial PLC I/O Module Identity |
Use Scenario: Saving undervoltage lockout (UVLO) thresholds, soft-start ramp rates, and fault recovery modes in DC-DC controllers. IC Role / Device Role / Timing Role: Configuration register backup for PMICs lacking internal NVM; accessed via SPI-to-Microwire bridge. Use Value: Allows single PMIC design to support multiple output configurations via EEPROM-programmed profiles. | Use Scenario: Storing unique MAC address, module revision ID, and channel mapping for distributed I/O nodes. IC Role / Device Role / Timing Role: Identity and configuration storage for hot-swappable modules in modular PLC backplanes. Use Value: Enables plug-and-play deployment with zero manual DIP-switch configuration or host-side setup. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar serial EEPROM applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| 93LC86B-I/SN | 1024 × 16-bit organization; same pinout, voltage, and timing-but outputs 16-bit words per READ. | Requires host firmware modification to handle 16-bit data framing and address alignment. | Select only if system architecture mandates 16-bit word access and memory map efficiency outweighs firmware porting effort. |
| AT25040B-MAHL-T | 4 Kbit SPI EEPROM (256 × 16); different interface (SPI vs Microwire), no Ready/Busy pin, 2.7–5.5V VCC. | Lacks hardware status signaling-requires fixed delay or polling via STATUS register; incompatible command set. | Choose only when migrating to SPI infrastructure and accepting loss of deterministic programming status feedback. |
Compared with 93LC86B-I/SN, the 93LC86A-I/SN provides native 8-bit word access without address remapping; compared with AT25040B-MAHL-T, it retains Microwire compatibility and hardware Ready/Busy signaling-critical for real-time deterministic programming in resource-constrained hosts.
Availability
93LC86A-I/SN is available at Aetrix Electronics and suitable for motor control configuration, smart sensor calibration, and power management IC settings requiring stable component supply across extended production lifecycles.
Supply support for 93LC86A-I/SN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Microchip Technology Inc. is a leading provider of microcontroller, analog, and Flash-IP solutions, serving industrial, automotive, and consumer markets with high-reliability semiconductor products.
The 93LCxx family was designed specifically for cost-sensitive, low-power serial EEPROM applications where Microwire compatibility, robust data retention, and industrial temperature operation are mandatory-targeting embedded systems with legacy controller interfaces.
FAQ
What is the memory organization of the 93LC86A-I/SN?
The 93LC86A-I/SN has a fixed 2048 × 8-bit (16 Kbit) organization with no ORG pin-unlike 'C' variants. It exclusively supports 8-bit word access. This eliminates external logic for word-size selection and simplifies PCB layout and firmware development for systems requiring byte-aligned storage.
Does the 93LC86A-I/SN support hardware write protection?
No-the 93LC86A-I/SN does not include a Program Enable (PE) pin or hardware write-protection feature. Write protection is implemented solely through the EWEN/EWDS instruction sequence. To prevent accidental writes, firmware must issue EWDS after each programming operation and avoid issuing EWEN unless intentional updates are required.
What is the maximum clock frequency supported by the 93LC86A-I/SN?
The 93LC86A-I/SN supports up to 3 MHz clock frequency when VCC ≥ 4.5V, 2 MHz at 2.5V ≤ VCC < 4.5V, and 1 MHz at 1.8V ≤ VCC < 2.5V. Since the 93LC86A-I/SN operates from 2.5V to 5.5V, its practical maximum is 3 MHz at 4.5–5.5V or 2 MHz across the full 2.5–4.5V range-enabling fast configuration loads in time-critical boot sequences.
How does the Ready/Busy status work on the 93LC86A-I/SN?
The DO pin of the 93LC86A-I/SN doubles as a Ready/Busy indicator during erase/write cycles: DO = low indicates ongoing programming; DO = high signals completion. To sample status, CS must be brought high for ≥250 ns after TCSL, then the host reads DO. After completion, issuing a Start bit followed by CS low clears the status flag-enabling deterministic polling without fixed delays.
Is the 93LC86A-I/SN RoHS compliant and lead-free?
Yes-the 93LC86A-I/SN is Pb-free and RoHS compliant, with a Matte Tin (Sn) finish on its 8-lead SOIC (SN) package. This meets EU Directive 2011/65/EU and is verified per Microchip's packaging specification. No lead-based soldering restrictions apply, and standard reflow profiles for Pb-free SOIC packages are fully supported.
93LC86A-I/SN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Microchip Technology
- Series:
- -
- Package/Case:
- 8-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Active
- Programmable:
- Not Verified
- Memory Type:
- Non-Volatile
- Memory Format:
- EEPROM
- Technology:
- EEPROM
- Memory Size:
- 16Kbit
- Memory Organization:
- 2K x 8
- Memory Interface:
- Microwire
- Clock Frequency:
- 3 MHz
- Write Cycle Time - Word, Page:
- 5ms
- Access Time:
- -
- Voltage - Supply:
- 2.5V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-SOIC
93LC86A-I/SN FAQ
1.How can I place an order for 93LC86A-I/SN through Aetrix?
Please submit a Request for Quotation (RFQ) for 93LC86A-I/SN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for 93LC86A-I/SN reliable?
The price and inventory of 93LC86A-I/SN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for 93LC86A-I/SN is usually 5 days.
3.What payment methods are accepted for 93LC86A-I/SN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for 93LC86A-I/SN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for 93LC86A-I/SN?
93LC86A-I/SN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your 93LC86A-I/SN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for 93LC86A-I/SN?
For technical support, including 93LC86A-I/SN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your 93LC86A-I/SN requirements.
6.How does Aetrix verify that 93LC86A-I/SN is sourced from the original manufacturer or authorized distributors?
All 93LC86A-I/SN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that 93LC86A-I/SN meets industry standards.
7.What is the process for return or replacement of 93LC86A-I/SN?
All 93LC86A-I/SN units undergo pre-shipment inspection (PSI). If there is an issue with 93LC86A-I/SN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The 93LC86A-I/SN part is unused and in its original packaging.
Return procedure for 93LC86A-I/SN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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