Microchip Technology 93LC86C-I/ST

Overview

93LC86C-I/ST from Microchip Technology is a 16 Kbit Microwire-compatible serial EEPROM with user-selectable 8-bit or 16-bit word organization via the ORG pin, program enable (PE) write protection, and industrial temperature range (–40°C to +85°C). It operates from 2.5V to 5.5V, supports self-timed erase/write cycles (5 ms typical), and delivers 1,000,000 endurance cycles with >200 years data retention - used in embedded system configuration storage, sensor calibration memory, and power-management parameter backup.

For engineers reviewing the 93LC86C-I/ST datasheet, 93LC86C-I/ST pinout, 93LC86C-I/ST application, or 93LC86C-I/ST equivalent, key selection considerations include VCC voltage compatibility (2.5–5.5 V), ORG/PE pin control logic for memory configuration and write lock, Ready/Busy status polling via DO, and package-specific layout requirements for the 8-lead TSSOP (ST) footprint.

Technical Context

The 93LC86C-I/ST implements a synchronous 3-wire Microwire interface (CS, CLK, DI/DO) with start-bit detection and opcode-driven command execution. Memory organization is dynamically selected: ORG = VSS enables 2048 × 8-bit mode; ORG = VCC enables 1024 × 16-bit mode. The PE pin must be driven high to permit erase/write operations - tied low disables all programming unconditionally.

Internal timing is fully self-timed: ERAL (Erase All) completes in 6 ms and WRAL (Write All) in 15 ms at VCC ≥ 4.5 V; standard WRITE/ERASE cycles require 5 ms. Status is reported on DO during active programming - low = busy, high = ready - and requires CS reassertion after TCSL ≥ 250 ns to sample.

Key Specifications

Pinout & Package

8-lead TSSOP (ST) package: 3.0 mm × 4.4 mm body, 0.65 mm pitch, exposed pad optional (not electrically connected). Pin 1 marked by laser dot; pin 1 ID corner located at top-left when notch faces up.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar serial EEPROM applications.

Compared with 93LC86C-I/SN and 93LC86C-I/MC, the 93LC86C-I/ST offers optimized surface-mount reliability and moderate thermal dissipation in a widely adopted TSSOP outline - ideal for automated assembly and mid-density industrial PCBs where SOIC is too large and DFN requires advanced process control.

Availability

93LC86C-I/ST is available at Aetrix Electronics and suitable for industrial automation, sensor module design, and embedded power management systems requiring stable component supply, long-lifecycle support, and RoHS-compliant packaging.

Supply support for 93LC86C-I/ST includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Microchip Technology Inc. is a leading provider of microcontrollers, analog devices, and memory solutions, headquartered in Chandler, Arizona, with global design and manufacturing operations.

The 93LC86C belongs to Microchip's legacy 93XX serial EEPROM family, designed specifically for cost-sensitive, low-power, nonvolatile storage in resource-constrained embedded systems where Microwire interface simplicity and hardware write protection are critical.

FAQ

What is the function of the ORG pin on the 93LC86C-I/ST?

The ORG pin on the 93LC86C-I/ST selects memory organization: tied to VSS it configures the device as 2048 × 8-bit; tied to VCC it configures as 1024 × 16-bit. This pin must be statically set before any instruction and cannot be changed dynamically during operation. Its presence distinguishes the 'C' variant from fixed-organization 'A' and 'B' versions.

How does the PE pin protect against accidental writes in the 93LC86C-I/ST?

The PE (Program Enable) pin on the 93LC86C-I/ST acts as a hardware write gate: only when PE is driven high can ERASE, WRITE, ERAL, or WRAL commands execute. If PE is tied low, all programming functions are permanently disabled - even if EWEN is issued. This provides fail-safe protection independent of firmware state or voltage glitches.

Can the 93LC86C-I/ST operate reliably at 2.5 V?

Yes, the 93LC86C-I/ST is fully specified down to 2.5 V: max clock frequency is 2 MHz, write current is ≤3 µA (standby), and TPD (data output delay) is ≤400 ns at CL = 100 pF. All DC and AC parameters in Table 1-1 and Table 1-2 are guaranteed across 2.5–5.5 V at –40°C to +85°C, making it suitable for single-cell Li-ion or energy-harvesting systems.

What is the purpose of the Ready/Busy status on the DO pin of the 93LC86C-I/ST?

The DO pin of the 93LC86C-I/ST serves dual function: during READ it outputs data; during ERASE/WRITE it signals Ready/Busy - low indicates ongoing self-timed operation, high confirms completion. To sample status, CS must be brought high for ≥250 ns after TCSL, then DO sampled on CLK edges. This eliminates need for fixed delay loops in host firmware.

Is the 93LC86C-I/ST pin-compatible with other 93XX86 variants in the same package?

Yes, the 93LC86C-I/ST shares identical 8-lead TSSOP (ST) pinout with all 93XX86A/B/C variants in that package - CS, CLK, DI, DO, VSS, ORG, PE, VCC occupy the same positions. However, ORG and PE are no-connection on 'A'/'B' parts, so PCBs designed for 93LC86C-I/ST remain compatible but must ensure those pins are not actively driven in 'A'/'B' drop-in scenarios.