NXP Semiconductors A2T21H360-24SR6
- Part No.:
- A2T21H360-24SR6
- Manufacturer:
- NXP Semiconductors
- Category:
- Single FETs, MOSFETs
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- -
- Datasheet:
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A2T21H360-24SR6.pdf
- Description:
- RF MOSFET LDMOS
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Product details
Overview
A2T21H360-24SR6 from NXP Semiconductors (formerly Freescale) is an asymmetrical Doherty RF power LDMOS transistor designed for carrier and peaking path amplification in cellular base station power amplifier stages. It delivers 63 W average output power at 2110–2170 MHz, operates at 28 Vdc supply, achieves 51.8% drain efficiency and 16.2 dB power gain under W-CDMA single-carrier conditions, and supports digital predistortion for linearized LTE/UMTS operation.
For engineers reviewing the A2T21H360-24SR6 datasheet, A2T21H360-24SR6 pinout, A2T21H360-24SR6 application, or A2T21H360-24SR6 equivalent, this page provides verified electrical specifications, thermal characteristics, Doherty-side functional roles, package mechanical data, and validated alternative options for macrocell and small-cell infrastructure designs.
Technical Context
The A2T21H360-24SR6 integrates two independent LDMOS devices-Carrier (Side A) and Peaking (Side B)-in a single NI-1230S-4L2L overmolded package. Side A is biased at IDQA = 500 mA with VGSA(Q) = 1.4–2.2 Vdc; Side B operates in Class C with VGSB = 0.5 Vdc, enabling high-efficiency back-off operation. Both sides are internally matched for 50 Ω systems across 2110–2170 MHz.
It implements advanced in-package Doherty architecture with separate RF input/output terminals per side and dedicated bias control pins (VBWA/VBWB). The device supports load mismatch tolerance up to VSWR 10:1 at 288 W pulse output and exhibits –28.8 dBc ACPR at ±5 MHz offset under 63 W avg. W-CDMA signal conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Frequency Range | 2110–2170 MHz - Covers full UMTS Band I and LTE Band 1 for cellular infrastructure. |
| Avg. Output Power | 63 W - Sustained average RF output under single-carrier W-CDMA with 9.9 dB PAR @ 0.01% CCDF probability. |
| Drain Efficiency | 51.8% typ. - Measured at 2140 MHz, 63 W avg., enabling reduced thermal load and power supply sizing. |
| Power Gain | 16.2 dB typ. - Small-signal to large-signal conversion ratio critical for PA linearity and driver stage sizing. |
| ACPR | –28.8 dBc @ ±5 MHz - Adjacent channel power rejection meeting 3GPP spectral mask requirements for Band I. |
| Thermal Resistance | 0.33 °C/W - Junction-to-case value measured at TC = 73°C, defining heatsink interface requirements. |
| VDD Rating | +32 Vdc max - Supports 28 Vdc nominal operation with margin for transient voltage spikes in base station supplies. |
| ESD Rating | HBM Class 2 - Withstands 2 kV human-body-model ESD events during handling and assembly. |
Pinout & Package
Package: NI-1230S-4L2L - Overmolded ceramic/metal flange-mount package with integral heat slug, 15.24 mm × 15.24 mm footprint, 4.57 mm height, and 4-layer internal leadframe optimized for RF grounding and thermal conduction.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (RFinA / VGSA) | Carrier gate input | RF and DC bias input for Carrier transistor; requires external DC blocking and matching network. |
| 2 (VBWA) | Carrier bias control | Adjustable negative/positive bias terminal for Carrier quiescent current setting (IDQA = 500 mA). |
| 3 (RFoutA / VDSA) | Carrier drain output | High-power RF output node for Carrier path; connects directly to output combiner network. |
| 4 (RFinB / VGSB) | Peaking gate input | RF and DC bias input for Peaking transistor; biased at 0.5 Vdc for Class C operation. |
| 5 (VBWB) | Peaking bias control | Bias adjustment terminal for Peaking side; enables fine-tuning of turn-on threshold and back-off behavior. |
| 6 (RFoutB / VDSB) | Peaking drain output | High-power RF output node for Peaking path; phase-aligned with Carrier output for Doherty combining. |
Key Features
| Feature | Design Value |
|---|---|
| Asymmetrical Doherty architecture | Enables >50% drain efficiency at 6–8 dB power back-off, reducing cooling and energy costs in deployed base stations. |
| Integrated input/output matching | Eliminates need for external broadband matching networks at 2110–2170 MHz, simplifying PCB layout and improving repeatability. |
| Negative VGS operating range | Supports deep Class C peaking operation with VGSB = 0.5 Vdc, extending efficiency enhancement to lower output power levels. |
| Digital predistortion (DPD) compatibility | Low AM/PM distortion (–27° max) and stable gain flatness (0.2 dB over 60 MHz) enable effective wideband DPD correction. |
| Tape-and-reel packaging (R6 suffix) | 150-unit reel on 56 mm tape width, 13-inch reel - optimized for automated SMT placement in high-volume infrastructure manufacturing. |
Applications
| Macrocell Base Station Transmitter | Remote Radio Head (RRH) |
|---|---|
Use Scenario: High-power final-stage PA in outdoor macrocell BTS covering 2110–2170 MHz for UMTS/LTE deployments. IC Role / Device Role / Timing Role: Dual-path Doherty RF power transistor delivering combined 63 W avg. output with digital predistortion support. Use Value: Achieves 51.8% drain efficiency at 63 W avg., reducing system-level power consumption and thermal management complexity. | Use Scenario: Compact, thermally constrained RRH unit requiring high-efficiency RF PA in tight form factor. IC Role / Device Role / Timing Role: Integrated Carrier + Peaking LDMOS die in single NI-1230S-4L2L package enables minimal external component count. Use Value: 0.33 °C/W RθJC allows direct mounting to aluminum cold plate without intermediate thermal interface layers. |
| Active Antenna System (AAS) | Multi-band MIMO Base Station |
Use Scenario: Active antenna array with integrated transceiver modules requiring high linearity and low ACPR. IC Role / Device Role / Timing Role: Final-stage PA element supporting W-CDMA/LTE signals with PAR = 9.9 dB and ACPR ≤ –28.8 dBc. Use Value: –28.8 dBc ACPR at ±5 MHz meets 3GPP TS 36.104 spectral emission limits for Category A base stations. | Use Scenario: Multi-channel MIMO base station using parallel A2T21H360-24SR6 units per sector. IC Role / Device Role / Timing Role: Identical Doherty PA core across channels ensures consistent gain, phase, and efficiency for beamforming calibration. Use Value: Gain variation ≤ 0.012 dB/°C and output power drift ≤ 0.002 dB/°C enable stable inter-channel coherence over temperature. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF power amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AFM360-24S | Same NI-1230S-4L2L package, identical 2110–2170 MHz frequency coverage, but rated for 40 W avg. output and lower P3dB (280 W vs. 400 W). | Suitable for lower-power RRH or indoor small cell where thermal budget is tighter and peak envelope power demand is reduced. | Select AFM360-24S when system-level output requirement is ≤40 W avg. and board space/thermal constraints favor same-footprint downrating. |
| CGHV1F025S | Gallium nitride (GaN) process; higher P1dB (320 W), wider bandwidth (1800–2400 MHz), but requires external input/output matching and different bias sequencing. | Used in next-gen massive MIMO and wideband active antenna systems needing broader instantaneous bandwidth and higher peak power. | Choose CGHV1F025S only when designing for GaN-specific benefits (e.g., >70% efficiency at 10 dB back-off) and can accommodate redesign of matching networks and bias control. |
Compared with AFM360-24S, the A2T21H360-24SR6 delivers +23 W avg. output and +120 W P3dB within identical footprint and thermal interface, while CGHV1F025S trades off matching simplicity and legacy LDMOS reliability for GaN's raw power density and bandwidth-requiring full circuit requalification.
Availability
A2T21H360-24SR6 is available at Aetrix Electronics and suitable for macrocell base stations, remote radio heads, active antenna systems, and multi-band MIMO infrastructure requiring stable component supply, long-lifecycle support, and qualified RF power performance.
Supply support for A2T21H360-24SR6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader focused on secure connectivity solutions for automotive, industrial, IoT, and communications infrastructure markets.
The A2T21H360-24SR6 belongs to the Airfast RF Power portfolio, engineered specifically for high-efficiency, digitally predistorted cellular base station power amplifiers operating in licensed sub-3 GHz spectrum bands.
FAQ
What is the maximum continuous drain voltage rating for the A2T21H360-24SR6?
The A2T21H360-24SR6 has a maximum drain-source voltage rating (VDSS) of +65 Vdc and –0.5 Vdc. This rating defines the absolute limit for safe DC operation; the device is typically operated at VDD = 28 Vdc in cellular base station applications. Exceeding +65 Vdc risks irreversible breakdown of the LDMOS structure, while negative voltage beyond –0.5 Vdc may cause gate oxide stress. The A2T21H360-24SR6 datasheet specifies these limits in Table 1 under Maximum Ratings.
Does the A2T21H360-24SR6 require external input and output matching networks?
No, the A2T21H360-24SR6 is internally matched for 50 Ω systems across its 2110–2170 MHz operating band. The device integrates optimized input and output impedance transformation within the NI-1230S-4L2L package, eliminating the need for discrete broadband matching components in standard Doherty configurations. However, external harmonic filters and isolation circuits remain necessary for system-level spectral compliance and stability. This internal matching is confirmed in the Functional Tests section of the A2T21H360-24SR6 datasheet.
What is the recommended gate bias for the peaking side (Side B) of the A2T21H360-24SR6?
The recommended gate bias for the peaking side (Side B) of the A2T21H360-24SR6 is VGSB = 0.5 Vdc under typical W-CDMA test conditions (VDD = 28 Vdc, IDQA = 500 mA, Pout = 63 W avg.). This low positive bias enables efficient Class C operation, allowing the peaking transistor to activate only during signal peaks and thereby extending high-efficiency operation into power back-off regions. The A2T21H360-24SR6 datasheet specifies this value in both the Functional Tests table and Figure 1 pin description.
How does the A2T21H360-24SR6 handle load mismatch conditions?
The A2T21H360-24SR6 is characterized for robust load mismatch tolerance: it withstands VSWR 10:1 at 28 Vdc with 288 W pulse output power and 3 dB input overdrive without degradation. This capability is validated using Freescale's Doherty test fixture and reflects the device's ability to sustain operation under antenna detuning or cable fault conditions common in deployed base stations. The A2T21H360-24SR6 datasheet documents this in the Load Mismatch section of Table 4.
What thermal interface material is recommended for mounting the A2T21H360-24SR6?
No specific thermal interface material is mandated for the A2T21H360-24SR6, but industry-standard thermal greases (e.g., Dow Corning TC-5122) or phase-change pads (e.g., Laird TPCM 600) with thermal conductivity ≥3.0 W/m·K are recommended to achieve the specified 0.33 °C/W junction-to-case thermal resistance. Mounting must ensure uniform pressure (≥50 psi) across the entire flange surface and use stainless steel hardware to prevent galvanic corrosion. These guidelines align with AN1955, referenced in the A2T21H360-24SR6 datasheet.
A2T21H360-24SR6 Specifications
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- NXP Semiconductors
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A2T21H360-24SR6 FAQ
1.How can I place an order for A2T21H360-24SR6 through Aetrix?
Please submit a Request for Quotation (RFQ) for A2T21H360-24SR6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A2T21H360-24SR6 reliable?
The price and inventory of A2T21H360-24SR6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A2T21H360-24SR6 is usually 5 days.
3.What payment methods are accepted for A2T21H360-24SR6?
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A2T21H360-24SR6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A2T21H360-24SR6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A2T21H360-24SR6?
For technical support, including A2T21H360-24SR6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A2T21H360-24SR6 requirements.
6.How does Aetrix verify that A2T21H360-24SR6 is sourced from the original manufacturer or authorized distributors?
All A2T21H360-24SR6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A2T21H360-24SR6 meets industry standards.
7.What is the process for return or replacement of A2T21H360-24SR6?
All A2T21H360-24SR6 units undergo pre-shipment inspection (PSI). If there is an issue with A2T21H360-24SR6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A2T21H360-24SR6 part is unused and in its original packaging.
Return procedure for A2T21H360-24SR6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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