My Inquiry
My Account
NXP Semiconductors A2V09H525-04NR6
- Part No.:
- A2V09H525-04NR6
- Manufacturer:
- NXP Semiconductors
- Category:
- Single FETs, MOSFETs
- Package:
- OM-1230-4L
- Datasheet:
-
A2V09H525-04NR6.pdf
- Description:
- RF MOSFET LDMOS 48V OM1230-4
- Quantity:
- Payment:
- Shipping:
Inventory:4,592
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
A2V09H525-04NR6 from NXP Semiconductors is a 120 W asymmetrical Doherty RF power LDMOS transistor designed for cellular base station amplifiers operating in the 720–960 MHz band. It delivers 18.9 dB power gain, 56.7% drain efficiency, and –32.4 dBc ACPR at 940 MHz under W-CDMA single-carrier conditions (Pout = 120 W Avg., VDD = 48 Vdc, IDQA = 688 mA).
For engineers reviewing the A2V09H525-04NR6 datasheet, A2V09H525-04NR6 pinout, A2V09H525-04NR6 application, or A2V09H525-04NR6 equivalent, this device supports digital predistortion (DPD) systems in macrocell and remote radio head (RRH) transmitters requiring high linearity, thermal robustness, and asymmetrical Doherty architecture.
Technical Context
The A2V09H525-04NR6 integrates two independent LDMOS cells-Carrier (Side A) and Peaking (Side B)-in a monolithic plastic package (OM-1230-4L), enabling true asymmetrical Doherty operation with separate gate bias control (VGSA/VGSB). Its internal input matching eliminates external input matching networks across 720–960 MHz.
It operates with dual gate biasing: VGSA(Q) = 2.5 Vdc (typ.) for the Carrier side and VGSB = 1.1 Vdc (typ.) for the Peaking side at 940 MHz, supporting Class AB/Class C hybrid operation. The exposed backside source terminal provides low-inductance thermal and RF grounding critical for high-power RF stability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Frequency Range | 720–960 MHz - Covers LTE Band 12/13/14/17/20/28 (700 MHz) and Band 8/3/2/5 (900 MHz) for global macrocell deployment. |
| Output Power (Avg) | 120 W - Sustained average output power under W-CDMA single-carrier signal with 9.9 dB PAR, enabling 2×2 MIMO 4G base stations. |
| Drain Efficiency (ηD) | 56.7% @ 940 MHz - Reduces heat dissipation and DC power consumption in high-density RRH modules. |
| Power Gain (Gps) | 18.9 dB @ 940 MHz - Enables reduced driver stage complexity and lower system-level gain distribution burden. |
| ACPR (3.84 MHz offset) | –32.4 dBc @ 940 MHz - Meets 3GPP ACLR requirements for LTE FDD/TDD without excessive DPD overhead. |
| Thermal Resistance (RθJC) | 0.23 °C/W - Supports compact heatsink designs with case temperature up to +150°C and junction limit of +225°C. |
| ESD Rating | HBM Class 2, CDM Class C3 - Ensures manufacturability in standard SMT assembly lines without special ESD handling. |
Pinout & Package
Package: OM-1230-4L - Thermally enhanced plastic overmolded package with exposed copper backside (source terminal), 4-pin configuration, RoHS-compliant, moisture sensitivity level 3 (peak reflow 260°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1: RFinA / VGSA | Carrier-side gate input | Bias and RF input node for Carrier amplifier; requires stable DC blocking and gate bias network (e.g., 2.5 V Q-point). |
| 2: RFinB / VGSB | Peaking-side gate input | Independent gate control for Peaking amplifier; biased at ~1.1 Vdc for Class C operation in Doherty mode. |
| 3: RFoutA / VDSA | Carrier-side drain output | High-current RF output node; connects to carrier output combiner and harmonic filtering network. |
| 4: RFoutB / VDSB | Peaking-side drain output | Asymmetrical peaking output; phase-aligned with Carrier output via external coupler (e.g., CMX09Q02) for Doherty combining. |
Key Features
| Feature | Design Value |
|---|---|
| Advanced in-package Doherty | Monolithic integration of matched Carrier and Peaking LDMOS cells eliminates inter-die coupling and layout sensitivity. |
| Extended negative VGS range | –6.0 Vdc rating enables deeper Class C peaking bias for improved efficiency compression behavior and bandwidth extension. |
| Digital predistortion (DPD) optimized | Linearized AM/PM response (–22° max at P3dB) and stable load-pull contours support real-time DPD convergence in field-deployed systems. |
| Thermally robust construction | 0.23 °C/W RθJC and 225°C max TJ allow operation in sealed outdoor enclosures without active cooling. |
| Internal input matching | Eliminates discrete input matching components across 720–960 MHz, reducing bill-of-materials and PCB area in multi-band RRH designs. |
Applications
| Macrocell Base Station Transmitter | Remote Radio Head (RRH) |
|---|---|
|
Use Scenario: High-power 4T4R LTE eNodeB transmitter covering Bands 13/14/28 (700 MHz) and Band 8 (900 MHz) in urban macro sites. IC Role / Device Role / Timing Role: Final-stage asymmetrical Doherty PA delivering 120 W avg. per antenna port with DPD correction. Use Value: 56.7% efficiency at 120 W reduces system power draw by >15% vs. legacy Class AB PAs, lowering OPEX and thermal management cost. |
Use Scenario: Compact, weatherized RRH unit mounted on cell tower with integrated digital front-end and analog PA stage. IC Role / Device Role / Timing Role: Dual-path RF power amplifier core enabling wide instantaneous bandwidth (40 MHz) and low latency DPD adaptation. Use Value: Internal input matching and OM-1230-4L package reduce RF layout complexity and enable <12 mm PCB height for pole-mounted RRH form factors. |
| Multi-Band Cellular Infrastructure | 5G NR Sub-1 GHz Layer |
|
Use Scenario: Dual-band (700/900 MHz) transceiver module supporting LTE-A carrier aggregation with shared PA resources. IC Role / Device Role / Timing Role: Reconfigurable Doherty PA operated across 758–803 MHz and 920–960 MHz bands using common bias and thermal infrastructure. Use Value: Gain flatness of 0.29 dB over 40 MHz bandwidth ensures consistent EVM across aggregated carriers without per-band calibration. |
Use Scenario: Standalone 5G NR coverage layer co-located with 4G in low-band spectrum (n5/n8/n20/n28), requiring backward-compatible PA design. IC Role / Device Role / Timing Role: High-efficiency final-stage amplifier supporting 5G NR 20 MHz channels with 8.5 dB PAR and 3GPP-compliant ACLR. Use Value: –32.4 dBc ACPR at 940 MHz meets 5G NR ACLR-1 requirement (–32 dBc) without additional post-filtering or DPD iteration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar RF power amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| AFM906S | Single-ended 120 W LDMOS (non-Doherty); 17.5 dB gain, 52% ηD @ 940 MHz; no separate peaking gate. | Suitable for simpler Class AB architectures where DPD linearity margin is less constrained. | Select when system-level DPD capability is limited or thermal budget allows higher dissipation. |
| A2V09H525-04N | Same die, tape-and-reel variant without R6 suffix (bulk packaging); identical electrical specs and pinout. | Used in high-volume automated assembly where reel-based feeding is not required. | Select for manual prototyping, small-batch builds, or evaluation board integration where reel logistics add cost. |
Compared with AFM906S and A2V09H525-04N, the A2V09H525-04NR6 uniquely delivers asymmetrical Doherty efficiency gains above back-off while maintaining full pin compatibility and thermal performance-enabling higher spectral efficiency in space-constrained macrocell and RRH deployments without redesigning the RF front-end topology.
Availability
A2V09H525-04NR6 is available at Aetrix Electronics and suitable for macrocell base stations, remote radio heads, multi-band cellular infrastructure, and 5G NR sub-1 GHz layers requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for A2V09H525-04NR6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and communications markets, with deep expertise in RF power technology.
The A2V09H525-04NR6 belongs to NXP's AIRFAST® RF Power LDMOS family, engineered specifically for energy-efficient, thermally robust, and digitally linearizable cellular infrastructure amplifiers operating below 1 GHz.
FAQ
What is the maximum junction temperature specification for the A2V09H525-04NR6?
The A2V09H525-04NR6 has a specified operating junction temperature range of –40°C to +225°C. This high TJ rating enables reliable operation in sealed outdoor enclosures and high-ambient environments typical of macrocell base stations. Derating curves and MTTF calculators are provided in NXP application note AN1955.
Does the A2V09H525-04NR6 require external input matching networks?
No-the A2V09H525-04NR6 is internally input-matched across its full 720–960 MHz operating band. This eliminates discrete input matching components, simplifies PCB layout, and improves repeatability in high-volume manufacturing. Output matching remains external and must be optimized per application per NXP load-pull data.
How is the peaking amplifier biased in the A2V09H525-04NR6 Doherty configuration?
The peaking side (Side B) of the A2V09H525-04NR6 is biased via the RFinB/VGSB pin at 1.1 Vdc (typ.) under W-CDMA test conditions at 940 MHz. This shallow Class C bias point enables efficient turn-on only during signal peaks, achieving the asymmetrical Doherty efficiency enhancement while maintaining linearity with DPD.
What thermal interface material is recommended for mounting the A2V09H525-04NR6?
NXP recommends solder reflow attachment per application note AN1907 for the A2V09H525-04NR6. The exposed copper backside serves as both thermal path and RF ground; thermal interface materials (TIMs) are not used-instead, the package is directly soldered to a thermally enhanced PCB pad or heatsink using lead-free reflow profiles compliant with IPC/JEDEC J-STD-020 (MSL3, 260°C peak).
Can the A2V09H525-04NR6 operate across both 700 MHz and 900 MHz bands simultaneously?
The A2V09H525-04NR6 supports broadband operation from 720–960 MHz but is not designed for simultaneous dual-band transmission. It can be tuned for either 758–803 MHz or 920–960 MHz bands using distinct output matching networks, as validated in NXP's test circuit documentation for each frequency range.
A2V09H525-04NR6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Series:
- -
- Package/Case:
- OM-1230-4L
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Technology:
- LDMOS
- Configuration:
- -
- Frequency:
- 720MHz ~ 960MHz
- Gain:
- 18.9dB
- Voltage - Test:
- 48 V
- Current Rating (Amps):
- 10µA
- Noise Figure:
- -
- Current - Test:
- 688 mA
- Power - Output:
- 120W
- Voltage - Rated:
- 105 V
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- OM-1230-4L
A2V09H525-04NR6 FAQ
1.How can I place an order for A2V09H525-04NR6 through Aetrix?
Please submit a Request for Quotation (RFQ) for A2V09H525-04NR6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A2V09H525-04NR6 reliable?
The price and inventory of A2V09H525-04NR6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A2V09H525-04NR6 is usually 5 days.
3.What payment methods are accepted for A2V09H525-04NR6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A2V09H525-04NR6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A2V09H525-04NR6?
A2V09H525-04NR6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A2V09H525-04NR6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A2V09H525-04NR6?
For technical support, including A2V09H525-04NR6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A2V09H525-04NR6 requirements.
6.How does Aetrix verify that A2V09H525-04NR6 is sourced from the original manufacturer or authorized distributors?
All A2V09H525-04NR6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A2V09H525-04NR6 meets industry standards.
7.What is the process for return or replacement of A2V09H525-04NR6?
All A2V09H525-04NR6 units undergo pre-shipment inspection (PSI). If there is an issue with A2V09H525-04NR6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A2V09H525-04NR6 part is unused and in its original packaging.
Return procedure for A2V09H525-04NR6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
A2V09H525-04NR6 Tags
-
3SK294(TE85L,F)
Toshiba Semiconductor and Storage
-
SAV-551+
Mini-Circuits
-
TAV2-501+
Mini-Circuits
-
CE3514M4-C2
CEL
-
AFT05MS004NT1
NXP USA Inc.
-
SAV-541+
Mini-Circuits
-
CE3512K2-C1
CEL
-
AFM907NT1
NXP Semiconductors
-
SKY65050-372LF
Skyworks Solutions Inc.
-
CE3520K3-C1
CEL
-
AFT09MS007NT1
NXP USA Inc.
-
AFT09MS015NT1
NXP USA Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
