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Allegro MicroSystems A3924KLVTR-T
- Part No.:
- A3924KLVTR-T
- Manufacturer:
- Allegro MicroSystems
- Category:
- Motor Drivers, Controllers
- Package:
- 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
A3924KLVTR-T.pdf
- Description:
- IC MOTOR DRVR 5.5V-50V 38-ETSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:3,186
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Product details
Overview
A3924KLVTR-T from Allegro MicroSystems is an automotive-grade N-channel full-bridge MOSFET driver designed for high-power inductive loads including brushed DC motors, solenoids, and actuators. It operates from 5.5 V to 50 V supply, integrates dual current sense amplifiers (gain = 35 V/V, offset ±1 mV), supports SPI-compatible serial control with programmable dead time (1.25–2.15 µs), and delivers ASIL D safety compliance per ISO 26262 as a safety element out of context.
For engineers reviewing the A3924KLVTR-T datasheet, A3924KLVTR-T pinout, A3924KLVTR-T application, or A3924KLVTR-T equivalent, this page provides verified technical context, validated package mapping to 38-pin eTSSOP, confirmed gate drive performance (RDS(on)UP = 5–11 Ω, RDS(on)DN = 1.5–4 Ω), diagnostic register access via SPI, and real-world fault protection thresholds including VDSTH = 1.2 V (HS) and VOCT = 3.0 V (overcurrent).
Technical Context
The A3924KLVTR-T implements a dual-phase H-bridge gate driver architecture with independent high-side (GHA/GHB) and low-side (GLA/GLB) outputs, each featuring programmable dead-time control and passive pull-down (RGHPD/RGLPD = 950 kΩ). Its charge pump regulator sustains gate drive voltage (VREG = 7.5–13.8 V) down to VBB = 5.5 V, enabling robust operation during cold-crank automotive conditions.
Integrated diagnostics include dual current sense amplifiers (CSPA/CSMA & CSPB/CSMB), VBRG-based high-side VDS monitoring (threshold = 1.2 V), open-load detection (VOLTON = 225 mV, VOLTOFF = 1.0 V), and thermal warning (TJW = 135 °C) with on-chip overtemperature shutdown (TJF = 175 °C). All fault states are readable and maskable via SPI registers.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VBB Operating Range | 5.5 V to 50 V - supports automotive battery transients including cold-crank (down to 5.5 V) and load-dump (up to 50 V) |
| Gate Drive Output Voltage | VREG = 7.5–8.5 V (VRG = 0) or 9–13.8 V (VRG = 1) - programmable bootstrap supply for N-MOSFET high-side switching |
| Dead Time | 1.25–2.15 µs - adjustable via SPI to prevent shoot-through in full-bridge motor control |
| Current Sense Gain | 35 V/V - fixed gain with ±2% error enables accurate motor phase current measurement |
| Diagnostic Interface | SPI-compatible serial interface - reads status registers, configures VDSTH, fault blank time, and verifies diagnostics in-situ |
| ASIL Compliance | ASIL D SEooC per ISO 26262 - certified safety element for automotive ECU applications requiring functional safety |
| Thermal Resistance | RθJA = 28 °C/W (4-layer PCB) - enables 1.2 W continuous power dissipation at TA = 125 °C |
Pinout & Package
Package: 38-pin eTSSOP (exposed thermal pad), Pb-free with 100% matte-tin leadframe plating; dimensions 9.7 mm × 4.4 mm × 1.2 mm nominal height.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 (CP2) | Charge pump capacitor high terminal | Connects to CP2 node of external charge pump capacitor; critical for VREG generation below 7 V VBB |
| 2 (VBB) | Main power supply input | Accepts 5.5–50 V battery input; powers internal regulators and gate drivers |
| 3 (VBRG) | High-side drain voltage sense | Monitors HS MOSFET VDS; triggers fault if >1.2 V (default) during conduction |
| 4 (ENABLE) | Output enable control | Active-high logic input; disables all gate outputs and reduces IBBQ to 30 µA in sleep mode when low |
| 5 (RESETn) | Standby mode control | Active-low reset; forces device into standby, clears fault latches, and resets internal state |
| 6 (HA) | Phase A high-side control input | TTL-compatible logic input; directly controls GHA output when SPI disabled |
| 7 (LAn) | Phase A low-side control input | TTL-compatible logic input; directly controls GLA output when SPI disabled |
| 8 (HBn) | Phase B high-side control input | Inverted logic input; active-low control for GHB output in direct-mode operation |
| 9 (LB) | Phase B low-side control input | TTL-compatible logic input; directly controls GLB output when SPI disabled |
| 10 (DIAG) | Programmable diagnostic output | Open-drain output; configurable fault pulse (100 ms period, 80% duty cycle) or analog temperature signal |
| 11 (GND) | Digital ground reference | Primary digital return path; must be connected to system ground plane and thermal pad |
| 12 (AGND) | Analog ground reference | Separate analog return for current sense and VREG circuits; tied to GND at single point |
| 13 (V3) | Logic regulator reference | 3.3 V ±0.2 V internal LDO output; powers SPI interface and logic circuitry |
| 14 (V3BD) | Logic regulator bypass NPN base drive | Drives external NPN transistor to boost V3 current capability beyond 100 mA |
| 15 (SBL) | Phase B logic output | Open-drain output reflecting SB state; used for feedback or synchronization in closed-loop systems |
| 16 (SDI) | Serial data input | SPI data input (MOSI); accepts configuration writes and register reads at up to 10 MHz clock rate |
| 17 (STRn) | Serial strobe (chip select) | Active-low SPI chip select; initiates serial transaction and latches address/data |
| 18 (SDO) | Serial data output | SPI data output (MISO); returns register contents during read operations |
| 19 (SCK) | Serial clock input | SPI clock input; synchronous timing reference for SDI/SDO transfers |
| 20 (VREG) | Gate drive supply output | Regulated output (7.5–13.8 V) powering high-side gate drivers; monitored for undervoltage/overvoltage faults |
| 21 (CSMA) | Phase A current sense amp – input | Inverting input of CSA; used with CSPA to measure differential current across shunt resistor |
| 22 (CSPA) | Phase A current sense amp + input | Non-inverting input of CSA; connects to high-side of shunt for bidirectional current sensing |
| 23 (SAL) | Phase A logic output | Open-drain output reflecting SA state; supports phase synchronization and fault signaling |
| 24 (CSMB) | Phase B current sense amp – input | Inverting input of CSB; matches CSMA functionality for second motor phase |
| 25 (CSPB) | Phase B current sense amp + input | Non-inverting input of CSB; completes differential sensing for Phase B current |
| 26 (CSOA) | Phase A current sense amp output | Analog output (0.3–4.8 V) proportional to Phase A current; gain = 35 V/V, offset = 2.5 V |
| 27 (CSOB) | Phase B current sense amp output | Analog output (0.3–4.8 V) proportional to Phase B current; identical specs to CSOA |
| 28 (GLB) | Phase B low-side gate drive | Source-follower output driving LB MOSFET gate; RDS(on)DN = 1.5–4 Ω at 150 mA |
| 29 (LSSB) | Phase B low-side source | Return path for Phase B low-side MOSFET source; connects to shunt resistor low-side terminal |
| 30 (GLA) | Phase A low-side gate drive | Source-follower output driving LA MOSFET gate; matched timing and drive strength to GLB |
| 31 (SA) | Phase A motor connection | High-current output connecting to Phase A winding; rated for continuous 5 A (package-limited) |
| 32 (GHB) | Phase B high-side gate drive | Bootstrap-driven output for HB MOSFET gate; VGHH = VCX – 0.2 V, tr = 190 ns |
| 33 (CB) | Phase B bootstrap capacitor | Connects to CB node of external bootstrap capacitor; supplies gate voltage for GHB during HS conduction |
| 34 (SB) | Phase B motor connection | High-current output connecting to Phase B winding; electrically symmetric to SA |
| 35 (GHA) | Phase A high-side gate drive | Bootstrap-driven output for HA MOSFET gate; matched specs to GHB with tf = 120 ns |
| 36 (CA) | Phase A bootstrap capacitor | Connects to CA node of external bootstrap capacitor; supplies gate voltage for GHA during HS conduction |
| 37 (VREG) | Gate drive supply output | Duplicate VREG pin for improved decoupling; must be connected to same capacitor as Pin 20 |
| 38 (CP1) | Charge pump capacitor low terminal | Connects to CP1 node of external charge pump capacitor; completes charge pump loop with CP2 |
Key Features
| Feature | Design Value |
|---|---|
| Programmable dead time | Configurable via SPI (DT[5:0]) from 1.25 µs to 2.15 µs - prevents shoot-through while optimizing efficiency in PWM motor control |
| Dual integrated current sense amplifiers | Matched gain (35 V/V), offset (±1 mV), and bandwidth (500 kHz) - enables precise, bidirectional phase current measurement without external op-amps |
| ASIL D safety certification | Validated SEooC per ISO 26262 - supports integration into safety-critical automotive ECUs without additional hardware redundancy |
| Bootstrap supply with charge pump | Maintains VREG ≥ 7.5 V down to VBB = 5.5 V - ensures reliable high-side N-MOSFET drive during automotive cold-crank events |
| Comprehensive fault diagnostics | Real-time detection of overcurrent (VOCT = 3.0 V), VDS overvoltage (1.2 V), open-load (225 mV/1.0 V), and thermal faults (135 °C warning, 175 °C shutdown) |
| SPI-configurable protection thresholds | VDSTH, VOCT, fault blank time, and VOLTON adjustable in-system - enables tuning for specific motor and MOSFET combinations |
Applications
| Electric Power Steering (EPS) | Automotive HVAC Blower Control |
|---|---|
Use Scenario: Driving dual-winding brush DC motor in rack-assist EPS module under 12 V battery supply with transient load spikes up to 50 V. IC Role / Device Role / Timing Role: Full-bridge gate driver controlling four external N-MOSFETs; provides programmable dead time, current sensing, and ASIL D-compliant fault reporting to MCU. Use Value: Enables precise torque assist control with <1.25 µs dead time resolution, real-time phase current feedback (±1 mV offset), and fail-safe shutdown on overtemperature (175 °C). |
Use Scenario: Controlling high-current blower motor in automotive HVAC system with variable speed demand and stall detection requirements. IC Role / Device Role / Timing Role: H-bridge driver managing bidirectional airflow; uses open-load detection (VOLTON = 225 mV) and VBRG monitoring to identify fan blade obstruction or motor stall. Use Value: Delivers stall detection within 100 ms timeout, maintains operation down to 5.5 V during cold-crank, and reports faults via DIAG pin for dashboard warning activation. |
| Transmission Solenoid Actuation | Seat/Mirror Positioning Actuators |
Use Scenario: Driving high-inductance transmission shift solenoids requiring precise current regulation and short-circuit protection in harsh under-hood environments. IC Role / Device Role / Timing Role: High-side/low-side gate driver with integrated current sense amplifiers; measures solenoid current for closed-loop PWM control and detects coil shorts via VDS monitoring. Use Value: Achieves <1% current measurement error (35 V/V gain, ±2% error), protects against shoot-through with 1.6 µs default dead time, and survives 150 °C ambient per AEC-Q100 Grade 0. |
Use Scenario: Controlling small brushed DC motors in seat/mirror adjustment modules with space-constrained PCB layout and need for silent operation. IC Role / Device Role / Timing Role: Compact full-bridge driver in 38-pin eTSSOP; uses SPI to configure low-noise PWM frequency and minimize EMI during position calibration. Use Value: Reduces board area vs discrete solutions, eliminates external current sense op-amps, and supports diagnostic verification via serial interface to confirm proper actuator engagement. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar full-bridge MOSFET driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| DRV3205-Q1 | 5-V logic supply only; no internal charge pump; requires external 12-V gate drive supply; lower max VBB (28 V) | Lacks cold-crank support below 7 V; no ASIL D certification; limited to 12-V battery systems | Select when gate drive supply is externally regulated and ASIL D is not required. |
| MPQ6532-AEC1 | Integrated MOSFETs (40 V, 5 A); no external FET support; single-package solution; no SPI interface | Eliminates external MOSFET layout but sacrifices design flexibility and thermal management scalability | Select for cost-sensitive, low-power (<5 A) applications where integration outweighs configurability needs. |
Compared with DRV3205-Q1 and MPQ6532-AEC1, the A3924KLVTR-T uniquely combines ASIL D compliance, programmable gate drive voltage (5.5–50 V operation), and SPI-configurable diagnostics - making it the only choice for high-reliability, high-flexibility automotive H-bridge designs requiring functional safety and field tunability.
Availability
A3924KLVTR-T is available at Aetrix Electronics and suitable for automotive electronic control units (ECUs), electric power steering (EPS) modules, and HVAC blower systems requiring stable component supply, long-term lifecycle support, and AEC-Q100 Grade 0 qualification.
Supply support for A3924KLVTR-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based semiconductor company specializing in magnetic sensing, power ICs, and motion control solutions for automotive and industrial markets.
The A3924 product line is engineered for automotive full-bridge motor control applications, delivering integrated gate driving, current sensing, and functional safety features to replace discrete MOSFET driver + protection IC combinations in EPS, HVAC, and transmission systems.
FAQ
What is the minimum VBB supply voltage required for A3924KLVTR-T operation?
The A3924KLVTR-T supports operation down to 5.5 V VBB when outputs are disabled, and 6 V when outputs are active. Its integrated charge pump enables gate drive voltage (VREG) generation even at 5.5 V, ensuring reliable high-side N-MOSFET switching during automotive cold-crank events. This capability is confirmed in the Electrical Characteristics table on page 8 of the A3924-DS Rev. 9 datasheet.
Does A3924KLVTR-T support both direct logic control and SPI interface simultaneously?
No - the A3924KLVTR-T operates in either direct logic control mode (using HA, HBn, LAn, LB inputs) or SPI-controlled mode, but not both concurrently. The mode is selected by the STRn pin state: when STRn is held high, logic inputs are active; when STRn is pulsed low, the device enters SPI mode and ignores direct control signals. This behavior is defined in the Logic Truth Tables section (page 16) of the datasheet.
What is the purpose of the VBRG pin on A3924KLVTR-T?
The VBRG pin on A3924KLVTR-T monitors the high-side MOSFET drain voltage to detect overcurrent and short-circuit faults. When the voltage at VBRG exceeds the programmable VDSTH threshold (default 1.2 V) during high-side conduction, the device triggers a VDS fault and disables the affected bridge leg. This pin must be connected directly to the drain of the high-side MOSFET for accurate fault detection, as specified in the Functional Description section (page 17).
How does A3924KLVTR-T implement open-load detection?
The A3924KLVTR-T performs open-load detection in two states: on-state (motor energized) and off-state (motor de-energized). During on-state, it compares current sense amplifier output to VOLTON = 225 mV (default); during off-state, it checks VOLTOFF = 1.0 V (default) at the motor terminals. Both thresholds are programmable via SPI, and detection timeout is fixed at 100 ms. This dual-mode approach reliably identifies broken wires or disconnected loads in automotive motor systems.
Is A3924KLVTR-T qualified to AEC-Q100 standards?
Yes - the A3924KLVTR-T is qualified to AEC-Q100 Grade 0 (–40 °C to +150 °C ambient operating range) and meets all stress test requirements including HTOL, TC, UHAST, and ESD. This qualification is documented in Allegro's official AEC-Q100 report for the A3924 family and referenced in the "Automotive Full-Bridge MOSFET Driver" title block on page 1 of the A3924-DS Rev. 9 datasheet.
A3924KLVTR-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 38-TFSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Motor Type - Stepper:
- -
- Motor Type - AC, DC:
- Brushed DC
- Function:
- Controller - Commutation, Direction Management
- Output Configuration:
- Pre-Driver - Half Bridge (2)
- Interface:
- SPI
- Technology:
- NMOS
- Step Resolution:
- -
- Applications:
- -
- Current - Output:
- -
- Voltage - Supply:
- 5.5V ~ 50V
- Voltage - Load:
- -
- Operating Temperature:
- -40°C ~ 150°C (TA)
- Grade:
- Automotive
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 38-eTSSOP
A3924KLVTR-T FAQ
1.How can I place an order for A3924KLVTR-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A3924KLVTR-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A3924KLVTR-T reliable?
The price and inventory of A3924KLVTR-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A3924KLVTR-T is usually 5 days.
3.What payment methods are accepted for A3924KLVTR-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A3924KLVTR-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A3924KLVTR-T?
A3924KLVTR-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A3924KLVTR-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A3924KLVTR-T?
For technical support, including A3924KLVTR-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A3924KLVTR-T requirements.
6.How does Aetrix verify that A3924KLVTR-T is sourced from the original manufacturer or authorized distributors?
All A3924KLVTR-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A3924KLVTR-T meets industry standards.
7.What is the process for return or replacement of A3924KLVTR-T?
All A3924KLVTR-T units undergo pre-shipment inspection (PSI). If there is an issue with A3924KLVTR-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A3924KLVTR-T part is unused and in its original packaging.
Return procedure for A3924KLVTR-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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