Allegro MicroSystems A3936SEDTR
- Part No.:
- A3936SEDTR
- Manufacturer:
- Allegro MicroSystems
- Category:
- Motor Drivers, Controllers
- Package:
- 44-LCC (J-Lead)
- Datasheet:
-
A3936SEDTR.pdf
- Description:
- IC MOTOR DRIVER 3V-5.5V 44PLCC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
A3936SEDTR from Allegro MicroSystems is a DMOS three-phase PWM motor driver IC designed for brushless DC (BLDC) motor control in industrial and automotive subsystems, delivering ±3 A peak output current at up to 50 V supply voltage with configurable slow/fast/mixed-decay current regulation and integrated synchronous rectification.
For engineers reviewing the A3936SEDTR datasheet, A3936SEDTR pinout, A3936SEDTR application, or A3936SEDTR equivalent, this device supports Hall-sensor-based commutation, tachometer feedback, thermal shutdown with hysteresis, UVLO protection, and external PWM enable-critical for precision BLDC speed and torque control in motion systems.
Technical Context
The A3936SEDTR implements fixed off-time PWM current control with programmable decay modes via PFD1/PFD2 inputs, enabling precise winding current regulation using an internal sense comparator referenced to VREF and blanked during switching transients via the BLANK input. Its oscillator frequency (typically 4 MHz) sets the 24 µs default off-time.
It integrates dual charge-pump circuitry (CP1/CP2/VCP) to drive high-side DMOS sources above VBB, and a linear regulator (VREG) to power low-side sinks, both internally monitored for fault shutdown. Hall-input logic (HA±/HB±/HC±) enables 120°-spaced commutation with DIR-controlled forward/reverse sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current Rating | ±3 A continuous - supports medium-power BLDC motors without external current amplification |
| Supply Voltage Range (VBB) | Up to 50 V - compatible with 24 V and 48 V industrial motor bus systems |
| rDS(on) (Source/Sink) | Typ. 500 mΩ / 315 mΩ - reduces conduction loss and thermal load in H-bridge outputs |
| Decay Mode Control | Configurable via PFD1/PFD2 - enables slow, fast, or mixed decay for optimized torque ripple and efficiency |
| Tachometer Output | Open-collector toggle per Hall transition - provides direct speed feedback for closed-loop control |
| Thermal Shutdown | 165 °C with 15 °C hysteresis - ensures safe recovery after overtemperature events without latch-up |
| UVLO Threshold | 2.45–2.95 V on VDD - prevents erratic operation during brown-out conditions |
Pinout & Package
The A3936SEDTR is housed in a 44-pin plastic leaded chip carrier (PLCC) package with internally fused ground leads (pins 1, 2, 44; 11, 12, 13; 22, 23, 24; 33, 34, 35) for enhanced thermal dissipation. The exposed power ground tab (pin 44) is electrically connected to GND and requires no isolation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (pins 1, 2, 11–13, 22–24, 33–35, 44) | Power and signal ground reference | Multiple fused GND pins provide low-impedance return paths and improved heat spreading |
| HA±, HB±, HC± (pins 3–8) | Hall-effect sensor inputs | Accept differential Hall signals for 120° electronic commutation of BLDC motors |
| OUTA/OUTB/OUTC (pins 17, 21, 28) | Three-phase half-bridge outputs | Drive motor windings in full H-bridge configuration with source/sink DMOS outputs |
| VBB1/VBB2 (pins 19, 26) | Motor supply inputs | Dual VBB connections reduce trace inductance and improve current sharing across high-side drivers |
| VCP/CP1/CP2 (pins 29–31) | Charge pump terminals | Generate gate drive voltage > VBB for high-side DMOS; require external 0.22 µF ceramic capacitors |
| SENSE (pin 15) | Current sense input | Connects to shunt resistor to set ITRIP = VREF/(10 × RSENSE); blanked during PWM transitions |
| TACH (pin 27) | Open-collector speed output | Provides square-wave tach signal synchronized to Hall transitions for RPM measurement |
| SLEEP (pin 32) | Low-power mode control | Pulling low disables all internal circuitry except bias, reducing quiescent current to <100 µA |
Key Features
| Feature | Design Value |
|---|---|
| Synchronous rectification (SR input) | Reduces power dissipation by replacing body-diode conduction with low-RDS(on) MOSFET conduction during decay |
| Programmable decay timing (PFD1/PFD2) | Enables fine-tuning of current recirculation path to minimize torque ripple and acoustic noise |
| Integrated charge pump & VREG | Eliminates need for external high-voltage gate drivers or auxiliary regulators in 3-phase BLDC designs |
| Crossover current protection | Prevents shoot-through by disabling both source and sink drivers during switching transitions |
| Brake function (BRAKE input) | Shorts motor phases to ground for rapid deceleration-bypasses current regulation but requires external current limiting |
Applications
| Industrial Pump Control | Automotive HVAC Blower |
|---|---|
|
Use Scenario: Closed-loop speed control of centrifugal pumps in HVAC and fluid handling systems. IC Role / Device Role / Timing Role: Three-phase BLDC motor driver with Hall-based commutation and tach feedback for RPM regulation. Use Value: Enables energy-efficient variable-speed operation with ±3 A drive capability and thermal shutdown for unattended operation. |
Use Scenario: Fan speed modulation in vehicle climate control units under wide ambient temperature ranges. IC Role / Device Role / Timing Role: Motor driver with UVLO, thermal hysteresis, and SLEEP mode for low-power standby states. Use Value: Supports ASIL-ready design with fault detection (TSD, UVLO, crossover protection) and 50 V bus tolerance for 24 V automotive systems. |
| Medical Infusion Pump | Factory Automation Conveyor |
|
Use Scenario: Precision dosing via constant-torque BLDC motor driving peristaltic pump mechanisms. IC Role / Device Role / Timing Role: Current-regulated motor driver with fixed off-time PWM and mixed-decay mode for smooth low-speed operation. Use Value: Delivers stable microstep-equivalent control without external controllers, leveraging internal zero-current detect and blanking. |
Use Scenario: Modular conveyor belt drives requiring robust motor control in dusty, high-vibration environments. IC Role / Device Role / Timing Role: High-reliability BLDC driver with fused GND leads for thermal management and EMI reduction. Use Value: 44-pin PLCC package with multiple ground pins improves mechanical stability and thermal performance on industrial PCBs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar three-phase BLDC motor driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| STSPIN32F0A | Integrated ARM Cortex-M0 MCU + gate drivers; requires external MOSFETs; no internal DMOS; supports FOC | Targets field-oriented control (FOC) systems needing digital control loop implementation | Choose STSPIN32F0A when firmware-based torque/speed control and sensorless operation are required |
| DRV8313 | 3-phase gate driver only (no internal MOSFETs); supports up to 60 V; includes current shunt amplifier and SPI interface | Designed for discrete MOSFET solutions with programmable decay and real-time diagnostics | Choose DRV8313 when higher voltage, external FET selection, or digital configuration via SPI is needed |
Compared with STSPIN32F0A and DRV8313, the A3936SEDTR offers fully integrated DMOS outputs, Hall-input logic, and analog current regulation-reducing BOM count and simplifying layout-but lacks embedded processing or digital configurability.
Availability
A3936SEDTR is available at Aetrix Electronics and suitable for industrial pump control, automotive HVAC blower systems, medical infusion devices, and factory automation conveyors requiring stable component supply despite its Last-Time-Buy status.
Supply support for A3936SEDTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based semiconductor company specializing in magnetic sensing and power ICs for motion control, safety-critical, and energy-efficient systems.
The A3936SEDTR belongs to Allegro's legacy motor driver product line, engineered specifically for Hall-commutated three-phase BLDC motors in cost-sensitive, thermally demanding industrial and automotive applications.
FAQ
What is the maximum operating voltage for the A3936SEDTR?
The A3936SEDTR supports a maximum load supply voltage (VBB) of 50 V, making it suitable for 24 V and 48 V motor bus architectures. This rating is absolute and must not be exceeded under any condition-including transient spikes-to avoid permanent damage. The logic supply (VDD) is limited to 7.0 V, with operational range specified from 4.5 V to 5.5 V for reliable control functionality. Both ratings are validated across the –20 °C to +85 °C ambient temperature range.
Does the A3936SEDTR include integrated MOSFETs or require external FETs?
The A3936SEDTR integrates fully realized DMOS power MOSFETs in a three-phase half-bridge configuration-no external FETs are required. Each phase (OUTA/OUTB/OUTC) contains matched source and sink DMOS devices with typical rDS(on) values of 500 mΩ (source) and 315 mΩ (sink), enabling direct connection to motor windings. This integration eliminates gate driver complexity and reduces PCB footprint versus gate-driver-only solutions like the DRV8313.
How does the A3936SEDTR implement current regulation?
The A3936SEDTR uses internal fixed off-time PWM current regulation based on a sense-resistor voltage (VSENSE) compared to a fraction of VREF. Trip current is calculated as ITRIP = VREF/(10 × RSENSE). When VSENSE reaches this threshold, the source driver turns off for a fixed 24 µs off-time (set by internal oscillator), after which decay mode (slow/fast/mixed) determines recirculation path. Blanking via BLANK input prevents false triggering from switching transients.
What Hall sensor interface configuration does the A3936SEDTR support?
The A3936SEDTR accepts differential Hall-effect inputs via six dedicated pins (HA±, HB±, HC±) arranged for 120° electrical spacing. It supports standard bipolar latching Hall sensors and interprets transitions to sequence six-step commutation. The HBIAS pin supplies bias current to the negative side of Hall elements. Commutation direction is controlled by the DIR input, and the truth table explicitly defines output states for forward/reverse rotation and idle conditions.
Is the A3936SEDTR pin-compatible with newer Allegro motor drivers?
No, the A3936SEDTR is not pin-compatible with newer Allegro motor drivers such as the A4964 or A5947. Its 44-pin PLCC (ED) package, Hall input arrangement, and dedicated control pin assignments (e.g., PFD1/PFD2 for decay mode, SR for synchronous rectification) are unique to this generation. Migration requires PCB redesign and firmware adaptation due to differences in register mapping, protection logic, and feature sets-even where functional overlap exists.
A3936SEDTR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 44-LCC (J-Lead)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Motor Type - Stepper:
- -
- Motor Type - AC, DC:
- Brushless DC (BLDC)
- Function:
- Driver - Fully Integrated, Control and Power Stage
- Output Configuration:
- Half Bridge (3)
- Interface:
- Parallel
- Technology:
- DMOS
- Step Resolution:
- -
- Applications:
- General Purpose
- Current - Output:
- 3A
- Voltage - Supply:
- 3V ~ 5.5V
- Voltage - Load:
- 9V ~ 50V
- Operating Temperature:
- -20°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 44-PLCC (16.59x16.59)
A3936SEDTR FAQ
1.How can I place an order for A3936SEDTR through Aetrix?
Please submit a Request for Quotation (RFQ) for A3936SEDTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A3936SEDTR reliable?
The price and inventory of A3936SEDTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A3936SEDTR is usually 5 days.
3.What payment methods are accepted for A3936SEDTR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A3936SEDTR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A3936SEDTR?
A3936SEDTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A3936SEDTR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A3936SEDTR?
For technical support, including A3936SEDTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A3936SEDTR requirements.
6.How does Aetrix verify that A3936SEDTR is sourced from the original manufacturer or authorized distributors?
All A3936SEDTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A3936SEDTR meets industry standards.
7.What is the process for return or replacement of A3936SEDTR?
All A3936SEDTR units undergo pre-shipment inspection (PSI). If there is an issue with A3936SEDTR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A3936SEDTR part is unused and in its original packaging.
Return procedure for A3936SEDTR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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