Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Motor Drivers, Controllers

Allegro MicroSystems A3946KLPTR

Name: A3946KLPTR
Brand: Allegro MicroSystems
SKU: A3946KLPTR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: A3946KLPTR

Manufacturer:: Allegro MicroSystems

Category:: Motor Drivers, Controllers

Package:: 16-TSSOP (0.173", 4.40mm Width) Exposed Pad

Datasheet:: A3946KLPTR.pdf

Description:: IC MOTOR DRIVER 7V-60V 16TSSOP

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:2,080

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

A3946KLPTR from Allegro MicroSystems is a half-bridge power MOSFET controller designed to drive high-current N-channel MOSFETs in unidirectional DC motor and three-phase BLDC motor applications. It features dual gate drivers (GH and GL), integrated top-off charge pump enabling 100% duty cycle operation, VREG output at 13 V nominal, and operates across –40°C to +135°C ambient temperature.

For engineers reviewing the A3946KLPTR datasheet, A3946KLPTR pinout, A3946KLPTR application, or A3946KLPTR equivalent, key selection criteria include bootstrap-enabled high-side drive capability, programmable dead time via DT pin, thermal shutdown at 170°C, undervoltage protection on VREG/BOOT/VREF, and compatibility with 7–60 V load supply voltage.

Technical Context

The A3946KLPTR implements a dual-output gate driver architecture with independent high-side (GH) and low-side (GL) outputs, each capable of sourcing/sinking ≥2 A peak current. Its internal top-off charge pump maintains high-side gate voltage during continuous conduction, eliminating shoot-through risk through configurable dead time (350 ns to 6 µs) set by external R_DEAD on DT pin.

Protection logic includes latched overtemperature shutdown (T_J = 170°C, 15°C hysteresis), VREG undervoltage lockout (8.3–9.1 V window), BOOT undervoltage detection (7.8–8.75 V), and open-drain ~FAULT reporting. Control modes support both single-pin PWM (IN1=IN2) and independent logic inputs with DT disabled via VREF tie.

Key Specifications

Parameter	Value and Actual Design Meaning
VBB Supply Range	7–60 V - supports wide automotive battery input including cold-crank and load-dump conditions.
VREG Output	13 V ±0.5 V @ 0–15 mA - powers low-side driver and bootstraps high-side circuitry.
Gate Drive Rise/Fall Time	60/40 ns typical @ 3300 pF - enables fast switching for high-efficiency motor control up to 100 kHz PWM.
Dead Time Range	350 ns to 6 µs - adjustable via R_DEAD (5–100 kΩ) to prevent cross-conduction in half-bridge topology.
Thermal Shutdown	170°C junction temperature with 15°C hysteresis - ensures safe operation under sustained overload or poor heatsinking.
Logic Input Thresholds	IN1/IN2 high ≥2.0 V, low ≤0.8 V with 100–300 mV hysteresis - robust against noise in automotive ECU environments.
Package Thermal Resistance	R_θJA = 34°C/W (4-layer JEDEC PCB) - enables >2 W dissipation without external heatsink in industrial motor drives.

Pinout & Package

Package: 16-lead TSSOP with exposed thermal pad (LP suffix), lead-free, matte tin-plated leadframe. Exposed pad must be soldered to PCB ground plane for thermal and EMI performance.

Pin/Terminal	Circuit Role	Design Meaning
VREG (1)	Regulated gate drive supply	13 V output powering GL driver and bootstrap capacitor charging path; requires 10 µF local decoupling.
CP2 (2), CP1 (3)	Charge pump capacitor terminals	Form external flying capacitor for VREG generation; CP1 tied to PGND, CP2 to VREG when active.
PGND (4)	Power ground reference	Separate from LGND; must connect directly to power return path near S pin to minimize switching noise coupling.
GL (5)	Low-side gate driver output	Sinks/source ≥2 A to drive N-MOSFET gate; series resistor controls dv/dt on S pin and EMI.
S (6)	Load connection / bootstrap return	Common node between motor/load and bootstrap capacitor negative; defines floating reference for GH driver.
GH (7)	High-side gate driver output	Drives N-MOSFET gate referenced to S; requires bootstrap capacitor (C_BOOT) for level-shifting.
BOOT (8)	Bootstrap capacitor positive terminal	Supplies gate voltage for GH; monitored for UVLO (7.8–8.75 V) to disable high-side during insufficient charge.
~FAULT (9)	Open-drain fault indicator	Pulled low on latched faults (OVERTEMP, UVREG) or transient faults (UVBOOT, UVREF); requires external pull-up.
IN1, IN2 (10–11)	Digital control inputs	Configure half-bridge state (H/L/brake); logic levels compatible with 3.3 V/5 V MCUs; 40 µA max input current.
RESET (12)	Global enable/disable	Active-low; forces sleep mode (<10 µA I_VBB) when held low >10 µs; clears latched faults on 1–10 µs pulse.
LGND (13)	Logic ground reference	Separate from PGND; connects to MCU/system ground to isolate digital noise from power switching paths.
DT (14)	Dead time programming input	Analog pin setting turn-on delay (350 ns–6 µs); grounded via R_DEAD for PWM mode; tied to VREF to disable dead time.
VREF (15)	Internal 5 V reference output	Stable 4.5–5.5 V source for external circuitry; max 4 mA load; requires 0.1 µF ceramic decoupling.
VBB (16)	Main power supply input	7–60 V input powering charge pump and internal regulators; quiescent current 3–6 mA in active mode.
PAD	Exposed thermal pad	Not electrically connected internally; must be soldered to large copper pour tied to PGND for thermal management.

Key Features

Feature	Design Value
Integrated top-off charge pump	Enables true 100% duty cycle high-side conduction without external boost supply or complex bootstrap timing.
Programmable dead time	Adjustable 350 ns–6 µs via single external resistor on DT pin, eliminating need for external timing ICs or FPGA logic.
Latched thermal shutdown	170°C trip with 15°C hysteresis prevents thermal runaway; fault persists until RESET pulse clears latch.
Dual independent ground pins	Separate PGND and LGND reduce noise coupling between power switching and logic domains in noisy motor systems.
VREG-regulated gate drive	13 V stable output ensures consistent MOSFET enhancement across VBB range (7–60 V), improving R_DS(on) margin.
Open-drain ~FAULT reporting	Single-wire diagnostic interface compatible with MCU GPIO interrupt inputs for real-time fault monitoring and recovery.

Applications

Automotive Power Seats	Industrial Conveyor Drives
Use Scenario: Bidirectional actuation of linear seat motors using H-bridge configuration with braking and soft-start. IC Role / Device Role / Timing Role: Half-bridge controller managing high-side and low-side N-MOSFETs to regulate current direction and magnitude in 12 V/24 V systems. Use Value: Integrated dead time and VREG regulation eliminate external gate drive biasing, reducing BOM count and layout complexity while meeting AEC-Q100 Grade 1 requirements.	Use Scenario: Speed-controlled AC induction motor starter using three-phase BLDC commutation with sensorless back-EMF sensing. IC Role / Device Role / Timing Role: Gate driver stage for inverter leg, synchronized with MCU PWM to deliver precise phase current waveforms. Use Value: Bootstrap + top-off charge pump sustains gate voltage during extended conduction periods, enabling smooth low-speed torque without gate droop.
Medical Infusion Pumps	Robotics Joint Actuators
Use Scenario: Precision micro-stepping of peristaltic pump motors requiring accurate current limiting and stall detection. IC Role / Device Role / Timing Role: Unidirectional DC motor controller with current sense interface (via ILIM pin) and fault-safe shutdown on overtemperature. Use Value: Latched thermal fault and VREG/BOOT UVLO ensure fail-safe motor stop during critical therapy delivery, supporting ISO 13485 design validation.	Use Scenario: High-bandwidth torque control of servo motors in collaborative robot arms with dynamic load reversal. IC Role / Device Role / Timing Role: High-frequency gate driver enabling >20 kHz PWM for low-acoustic-noise operation and rapid current loop response. Use Value: 60 ns rise time and 40 ns fall time minimize switching losses at 48 V bus, extending battery life and reducing thermal derating in compact enclosures.

Automotive Power Seats

Industrial Conveyor Drives

Use Scenario: Bidirectional actuation of linear seat motors using H-bridge configuration with braking and soft-start.

IC Role / Device Role / Timing Role: Half-bridge controller managing high-side and low-side N-MOSFETs to regulate current direction and magnitude in 12 V/24 V systems.

Use Value: Integrated dead time and VREG regulation eliminate external gate drive biasing, reducing BOM count and layout complexity while meeting AEC-Q100 Grade 1 requirements.

Use Scenario: Speed-controlled AC induction motor starter using three-phase BLDC commutation with sensorless back-EMF sensing.

IC Role / Device Role / Timing Role: Gate driver stage for inverter leg, synchronized with MCU PWM to deliver precise phase current waveforms.

Use Value: Bootstrap + top-off charge pump sustains gate voltage during extended conduction periods, enabling smooth low-speed torque without gate droop.

Medical Infusion Pumps

Robotics Joint Actuators

Use Scenario: Precision micro-stepping of peristaltic pump motors requiring accurate current limiting and stall detection.

IC Role / Device Role / Timing Role: Unidirectional DC motor controller with current sense interface (via ILIM pin) and fault-safe shutdown on overtemperature.

Use Value: Latched thermal fault and VREG/BOOT UVLO ensure fail-safe motor stop during critical therapy delivery, supporting ISO 13485 design validation.

Use Scenario: High-bandwidth torque control of servo motors in collaborative robot arms with dynamic load reversal.

IC Role / Device Role / Timing Role: High-frequency gate driver enabling >20 kHz PWM for low-acoustic-noise operation and rapid current loop response.

Use Value: 60 ns rise time and 40 ns fall time minimize switching losses at 48 V bus, extending battery life and reducing thermal derating in compact enclosures.

Equivalent & Alternatives

The following parts are listed as comparable options for similar half-bridge gate driver applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
MP6542GQ-Z	40 V max V_BB, no integrated charge pump - requires external bootstrap diode and capacitor; lacks top-off function for 100% duty cycle.	Best suited for lower-voltage (<40 V), intermittent-duty applications where full conduction is not required.	Select MP6542GQ-Z only if system V_BB stays below 40 V and duty cycle remains <95%; verify external bootstrap design for reliability.
TBD62783AFNG	Integrated high-side driver uses P-channel MOSFET - no bootstrap needed but higher R_DS(on); max V_BB = 36 V, no VREG output.	Ideal for cost-sensitive, low-power (<10 A) applications where efficiency is secondary to simplicity.	Choose TBD62783AFNG for fixed 24 V systems with modest current demands; avoid where high-side conduction loss or 60 V transients exist.

Compared with MP6542GQ-Z and TBD62783AFNG, the A3946KLPTR uniquely delivers 60 V operation, integrated top-off charge pump for true DC high-side drive, and 13 V regulated VREG - making it the only option among the three qualified for automotive-grade 12/24 V systems requiring robust, latchable fault handling and thermal resilience to 135°C ambient.

Availability

A3946KLPTR is available at Aetrix Electronics and suitable for automotive power seats, industrial conveyor drives, medical infusion pumps, and robotics joint actuators requiring stable component supply, AEC-Q100 compliance, and long-term production continuity.

Supply support for A3946KLPTR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Allegro MicroSystems is a U.S.-based semiconductor company specializing in high-performance magnetic sensing and precision power ICs for automotive and industrial motion control.

The A3946 product line delivers robust half-bridge gate drivers optimized for high-reliability motor control in harsh environments, with emphasis on thermal resilience, fault diagnostics, and simplified system-level design.

FAQ

What is the maximum allowable VBB voltage for the A3946KLPTR?

The A3946KLPTR supports a maximum load supply voltage (VBB) of 60 V, as specified in its Absolute Maximum Ratings table. This rating allows operation across automotive 12 V and 24 V systems, including transient conditions like load dump. Exceeding 60 V risks permanent damage to internal charge pump and gate driver circuits. Always maintain VBB within 7–60 V for reliable A3946KLPTR functionality and longevity.

How does the A3946KLPTR achieve 100% duty cycle operation for the high-side MOSFET?

The A3946KLPTR achieves 100% duty cycle high-side conduction using an internal top-off charge pump that replenishes charge lost from the bootstrap capacitor during sustained on-time. Unlike basic bootstrap drivers, this low-current trickle pump activates after GH turn-on to maintain V_BOOT above UVLO threshold (≥7.8 V), preventing gate voltage droop. The A3946KLPTR's architecture eliminates the need for external boost supplies or complex timing circuits to sustain DC conduction.

What happens when the ~FAULT pin goes low on the A3946KLPTR?

When the ~FAULT pin on the A3946KLPTR goes low, it indicates an active fault condition - either latched (OVERTEMP, UVREG) or transient (UVBOOT, UVREF). Latched faults persist until cleared by a 1–10 µs low pulse on RESET; transient faults clear automatically when the root cause resolves. During ~FAULT assertion, GH and GL outputs are disabled except in thermal shutdown, where they remain functional but require external intervention to prevent damage. The A3946KLPTR's ~FAULT behavior is fully documented in its Fault Response Table.

Can the A3946KLPTR drive both high-side and low-side N-channel MOSFETs simultaneously?

No - the A3946KLPTR is designed to prevent simultaneous conduction of high-side and low-side N-channel MOSFETs. Its control logic and programmable dead time (350 ns–6 µs) enforce a mandatory off-interval between GH and GL transitions to avoid shoot-through. The Control Logic Table explicitly shows "CAUTION: High-side and low-side FETs ON" only when IN1=IN2=VREF and DT=VREF - a prohibited configuration. Safe operation requires proper dead time configuration and adherence to the truth table in the A3946KLPTR datasheet.

What is the purpose of separate PGND and LGND pins on the A3946KLPTR?

The A3946KLPTR uses separate PGND (Pin 4) and LGND (Pin 13) pins to isolate high-current power return paths from low-noise logic reference planes. PGND carries switching currents from GL/GH drivers and must connect directly to the S pin ground plane; LGND serves digital inputs (IN1/IN2/RESET/DT) and should tie to MCU/system ground. This separation minimizes noise coupling into control signals, improves noise immunity in motor drive applications, and is essential for stable A3946KLPTR operation in electrically noisy environments.

A3946KLPTR Specifications

Product attributes: Attribute value

Manufacturer:: Allegro MicroSystems

Series:: -

Package/Case:: 16-TSSOP (0.173", 4.40mm Width) Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Motor Type - Stepper:: -

Motor Type - AC, DC:: Brushless DC (BLDC)

Function:: Controller - Commutation, Direction Management

Output Configuration:: Pre-Driver - Half Bridge

Interface:: Parallel

Technology:: Power MOSFET

Step Resolution:: -

Applications:: General Purpose

Current - Output:: -

Voltage - Supply:: 7V ~ 60V

Voltage - Load:: -

Operating Temperature:: -40°C ~ 135°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-eTSSOP-EP

A3946KLPTR FAQ

1.How can I place an order for A3946KLPTR through Aetrix?

Please submit a Request for Quotation (RFQ) for A3946KLPTR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for A3946KLPTR reliable?

The price and inventory of A3946KLPTR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A3946KLPTR is usually 5 days.

3.What payment methods are accepted for A3946KLPTR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A3946KLPTR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for A3946KLPTR?

A3946KLPTR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your A3946KLPTR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for A3946KLPTR?

For technical support, including A3946KLPTR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A3946KLPTR requirements.

6.How does Aetrix verify that A3946KLPTR is sourced from the original manufacturer or authorized distributors?

All A3946KLPTR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A3946KLPTR meets industry standards.

7.What is the process for return or replacement of A3946KLPTR?

All A3946KLPTR units undergo pre-shipment inspection (PSI). If there is an issue with A3946KLPTR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The A3946KLPTR part is unused and in its original packaging.

Return procedure for A3946KLPTR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…