Allegro MicroSystems A3949SLP-T
- Part No.:
- A3949SLP-T
- Manufacturer:
- Allegro MicroSystems
- Category:
- Motor Drivers, Controllers
- Package:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
A3949SLP-T.pdf
- Description:
- IC MOTOR DRIVER 8V-36V 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
A3949SLP-T from Allegro MicroSystems is a discontinued DMOS full-bridge motor driver IC designed for PWM-controlled DC motors, delivering ±2.8 A peak output current at up to 36 V supply voltage, with PHASE/ENABLE control interface and internal synchronous rectification for reduced power loss in industrial actuators and automotive seat/mirror modules.
For engineers reviewing the A3949SLP-T datasheet, A3949SLP-T pinout, A3949SLP-T application, or A3949SLP-T equivalent, key selection considerations include its LB-package thermal resistance (52 °C/W), sleep-mode quiescent current (≤10 μA), UVLO threshold (6 V), crossover delay (500 ns), and internal charge pump architecture requiring CP1/CP2 and VCP decoupling.
Technical Context
The A3949SLP-T implements a four-switch DMOS H-bridge with independent source/sink gate drive, where VCP powers high-side gates via an internal charge pump and VREG supplies low-side gates. It supports forward/reverse/brake/fast-decay SR modes via MODE, PHASE, ENABLE, and SLEEP logic inputs.
Protection includes thermal shutdown at 170 °C with 15 °C hysteresis, undervoltage lockout on VBB (6 V enable, 250 mV hysteresis) and VCP/VREG monitoring, plus crossover current protection and internal synchronous rectification control to minimize conduction losses during PWM decay phases.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Peak Output Current | ±2.8 A - supports medium-power DC motors without external current sensing or heatsinking under typical duty cycles |
| Supply Voltage Range | 8–36 V - compatible with 12 V and 24 V industrial and automotive battery systems |
| RDS(ON) (Sink, 25°C) | 0.3 Ω typ - limits I²R loss to ≤2.35 W per channel at 2.8 A, enabling compact PCB layout |
| RDS(ON) (Source, 25°C) | 0.4 Ω typ - ensures balanced conduction loss across bridge legs with synchronous rectification |
| UVLO Threshold | 6 V rising - prevents erratic operation during brown-out conditions in vehicle electrical systems |
| Thermal Shutdown | 170 °C junction - protects against latch-up during sustained overload or poor heatsinking |
| Sleep Current | ≤10 μA - enables ultra-low-power standby in battery-operated motor control nodes |
Pinout & Package
The A3949SLP-T is supplied in a 16-pin SOICW package with copper batwing tab (suffix LB), lead-free with 100% matte tin leadframes, JEDEC MS-013 AA compliant, and internally fused pins 4 (SLEEP) and 13 (VCP).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | N/C | No internal connection; must be left unconnected or tied to GND per layout guidelines |
| 2 | MODE | Selects decay mode (slow/fast) and braking behavior; critical for EMI and torque ripple control |
| 3, 12 | GND | Power ground return path for motor current and logic; requires low-inductance PCB plane |
| 4 | SLEEP | Active-high logic input; disables charge pump and VREG to reduce quiescent current to ≤10 μA |
| 5 | ENABLE | Global PWM enable/disable; sets outputs to Hi-Z when low, overriding PHASE/MODE states |
| 6, 9 | OUTA / OUTB | H-bridge output terminals; connect directly to motor leads; require external flyback protection |
| 7 | SENSE | Current-sense return node; used with external sense resistor for overcurrent detection |
| 8 | VBB | Main motor supply input (8–36 V); must be decoupled with ≥100 μF bulk + 0.1 μF ceramic |
| 10, 11 | CP1 / CP2 | Charge pump oscillator terminals; require 0.1 μF ceramic capacitor between them for gate drive boost |
| 13 | VCP | Charge pump reservoir; monitored for fault; requires 0.1 μF ceramic to VBB |
| 14 | VREG | Low-side gate supply output; requires 0.22 μF decoupling to GND for stable sink-driver operation |
Key Features
| Feature | Design Value |
|---|---|
| Internal Synchronous Rectification | Reduces power dissipation during PWM off-time by replacing body diode conduction with active low-RDS(ON) switch paths |
| Integrated Charge Pump | Enables high-side N-channel MOSFET drive without external bootstrap circuitry or timing constraints |
| Programmable Decay Mode | MODE pin selects slow decay (braking) or fast decay with synchronous rectification for optimized torque and EMI |
| Comprehensive Fault Protection | Independent monitoring of VBB, VCP, VREG, and junction temperature disables outputs before damage occurs |
| Ultra-Low Sleep Current | ≤10 μA quiescent draw allows integration into always-on systems such as automotive body controllers |
Applications
| Automotive Seat Adjustment | Industrial Linear Actuators |
|---|---|
Use Scenario: Precise bidirectional positioning of powered vehicle seats using 12 V DC motors. IC Role / Device Role / Timing Role: Full-bridge motor driver executing PHASE/ENABLE PWM commands from MCU, managing direction, speed, and braking. Use Value: Internal synchronous rectification reduces heat generation during frequent stop/start cycles, extending actuator lifetime. | Use Scenario: Controlled extension/retraction of factory automation linear slides driven by 24 V DC motors. IC Role / Device Role / Timing Role: H-bridge interface translating PLC or microcontroller PWM signals into motor phase control with fast-decay SR. Use Value: 52 °C/W thermal resistance and 170 °C thermal shutdown allow reliable operation in enclosed control cabinets without forced air cooling. |
| Medical Bed Positioning | Smart Home Window Blinds |
Use Scenario: Quiet, smooth height and tilt adjustment of hospital beds using low-inertia DC motors. IC Role / Device Role / Timing Role: Motor driver implementing slow-decay braking via MODE pin to prevent mechanical jerk during stops. Use Value: Crossover delay of 500 ns prevents shoot-through during direction reversal, ensuring patient safety and system reliability. | Use Scenario: Battery-powered motorized window coverings requiring multi-year operation on primary cells. IC Role / Device Role / Timing Role: Low-quiescent driver enabling sleep mode between position adjustments to conserve energy. Use Value: ≤10 μA sleep current extends CR123A battery life beyond 3 years in intermittent-use applications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar full-bridge motor driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| A3950SLPTR-T | Higher RDS(ON) (0.55 Ω sink, 0.7 Ω source), same LB package, identical pinout, extended temperature range (–40 to 150 °C) | Supports higher ambient temperatures in engine bay or industrial enclosures; lower efficiency at 2.8 A | Preferred for new designs requiring extended temp rating and drop-in replacement where thermal margin permits |
| TB6612FNG | Lower peak current (±1.2 A), smaller HTSSOP-20 package, no internal charge pump (requires external bootstrap), 2.7–10 V logic supply | Targeted at low-power robotics and portable devices; incompatible with 24 V motor supplies without level-shifting | Consider only for space-constrained, low-current (<1.2 A), dual-motor applications with separate logic supply |
Compared with A3949SLP-T, A3950SLPTR-T offers improved thermal robustness but reduced conduction efficiency, while TB6612FNG trades current capability and voltage range for footprint reduction and dual-channel integration-neither is pin-compatible, but both serve overlapping motion-control functions with distinct design trade-offs.
Availability
A3949SLP-T is available at Aetrix Electronics and suitable for legacy repair, end-of-life component consolidation, and industrial equipment maintenance requiring stable component supply for automotive seat modules, medical bed actuators, and smart home motorized blinds.
Supply support for A3949SLP-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer and manufacturer of high-performance magnetic sensors and power ICs, headquartered in Worcester, Massachusetts.
The A3949SLP-T belongs to Allegro's DMOS full-bridge motor driver product line, engineered for cost-sensitive, thermally constrained DC motor control in automotive body electronics and industrial motion systems.
FAQ
What is the recommended decoupling capacitance for the A3949SLP-T VCP pin?
The A3949SLP-T VCP pin requires a 0.1 μF ceramic monolithic capacitor connected between VCP and VBB to serve as a reservoir for high-side gate drive. This value is specified in the functional description section of the datasheet and ensures stable charge pump operation during PWM switching. Failure to install this capacitor may cause high-side driver dropout and unpredictable motor behavior. The A3949SLP-T datasheet explicitly mandates this value and does not permit substitution with larger or electrolytic types.
Can the A3949SLP-T be used in new designs despite its discontinued status?
No-the A3949SLP-T is officially discontinued per Allegro's product status notice dated June 2, 2014, and is not recommended for new designs. Samples are no longer available, and production has ceased. For new applications, Allegro recommends the A3950SLPTR-T as a direct functional upgrade. The A3949SLP-T remains supported only for legacy repair and maintenance where existing inventory or authorized surplus sources are verified.
How does the A3949SLP-T implement synchronous rectification?
The A3949SLP-T uses internal control logic to actively turn on the appropriate low-side DMOS transistor during the off-time of PWM cycles, replacing body-diode conduction with low-RDS(ON) channel conduction. This reduces power loss and heat generation, especially at high duty cycles. The feature is automatic and enabled by default-no external configuration is required. The A3949SLP-T datasheet confirms this behavior applies across all decay modes and is integral to its thermal performance specification.
What is the function of the SLEEP pin on the A3949SLP-T?
The SLEEP pin on the A3949SLP-T is an active-high logic input that disables the internal charge pump, VREG regulator, and most bias circuitry to reduce quiescent current to ≤10 μA. A logic low forces the device into ultra-low-power standby; a logic high restores normal operation. After exiting sleep mode, the A3949SLP-T requires a minimum 1 ms stabilization delay before applying PWM signals to ensure charge pump voltage settles. This timing is documented in the functional description section of the A3949SLP-T datasheet.
Does the A3949SLP-T support fast-decay braking with synchronous rectification?
Yes-the A3949SLP-T supports fast-decay braking with synchronous rectification (SR) when the MODE pin is set low and ENABLE is pulsed. In this configuration, both high- and low-side switches are actively controlled to recirculate current through the motor windings with minimal voltage drop, reducing heat and improving response time. The A3949SLP-T datasheet defines this behavior in the Control Logic Table and Functional Description sections, confirming it avoids body-diode conduction during decay phases.
A3949SLP-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Motor Type - Stepper:
- -
- Motor Type - AC, DC:
- Brushed DC
- Function:
- Driver - Fully Integrated, Control and Power Stage
- Output Configuration:
- Half Bridge (2)
- Interface:
- Parallel
- Technology:
- DMOS
- Step Resolution:
- -
- Applications:
- General Purpose
- Current - Output:
- 2.8A
- Voltage - Supply:
- 8V ~ 36V
- Voltage - Load:
- 8V ~ 36V
- Operating Temperature:
- -20°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-eTSSOP-EP
A3949SLP-T FAQ
1.How can I place an order for A3949SLP-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A3949SLP-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A3949SLP-T reliable?
The price and inventory of A3949SLP-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A3949SLP-T is usually 5 days.
3.What payment methods are accepted for A3949SLP-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A3949SLP-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A3949SLP-T?
A3949SLP-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A3949SLP-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A3949SLP-T?
For technical support, including A3949SLP-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A3949SLP-T requirements.
6.How does Aetrix verify that A3949SLP-T is sourced from the original manufacturer or authorized distributors?
All A3949SLP-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A3949SLP-T meets industry standards.
7.What is the process for return or replacement of A3949SLP-T?
All A3949SLP-T units undergo pre-shipment inspection (PSI). If there is an issue with A3949SLP-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A3949SLP-T part is unused and in its original packaging.
Return procedure for A3949SLP-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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