Allegro MicroSystems A3959SLP-T
- Part No.:
- A3959SLP-T
- Manufacturer:
- Allegro MicroSystems
- Category:
- Motor Drivers, Controllers
- Package:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Datasheet:
-
A3959SLP-T.pdf
- Description:
- IC MOTOR DRVR 4.5V-5.5V 28TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,771
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
A3959SLP-T from Allegro MicroSystems is a DMOS full-bridge PWM motor driver IC designed for bidirectional DC motor control with ±3 A output current and 50 V load supply capability. It implements internal fixed off-time current regulation, synchronous rectification, and selectable slow/fast/mixed decay modes via PFD1/PFD2 inputs. Used in industrial actuators, robotic joints, and precision motion systems where thermal efficiency and precise current limiting are critical.
For engineers reviewing the A3959SLP-T datasheet, A3959SLP-T pinout, A3959SLP-T application, or A3959SLP-T equivalent, this page provides verified package mapping (28-pin TSSOP-LP), confirmed pin functions (e.g., PHASE, ENABLE, PFD1, PFD2, SENSE), thermal resistance (RθJA = 40°C/W on 2-layer PCB), and real-world decay-mode timing behavior - all extracted from Allegro's official Rev. 14 datasheet.
Technical Context
The A3959SLP-T integrates dual DMOS H-bridge outputs with independent gate drive for source/sink paths, regulated by an internal 4.25 MHz oscillator (ROSC-dependent) and fixed 24 µs off-time. Current sensing uses external RS and internal 10× reference divider (VREF/10) to set ITRIP = VREF/(10·RS), with blanking timed at 6/fOSC or 12/fOSC based on BLANK input.
Thermal protection activates at TJ = 165°C with 15°C hysteresis; UVLO triggers at VDD = 4.2 V (±0.25 V); crossover-current protection prevents shoot-through during switching transitions. Synchronous rectification enables low-loss current recirculation by activating appropriate DMOS pairs during decay, reducing power dissipation versus body-diode conduction.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | ±3 A continuous (repetitive), ±6 A peak <3 µs - defines maximum motor winding current before thermal shutdown or current-limit activation |
| Load Supply Voltage | 9.5–50 V - supports wide-range DC motors including 12 V, 24 V, and 48 V industrial systems |
| rDS(on) | 270 mΩ typical per channel - determines conduction loss (I²R) and junction temperature rise under load |
| Fixed Off-Time | 24 µs typical (96 oscillator cycles @ 4.25 MHz) - sets minimum current-decay duration and regulates average current ripple |
| Thermal Resistance | RθJA = 40°C/W (2-layer PCB, 1-in² copper) - used to calculate junction temperature rise: ΔTJ = PD × RθJA |
| Current Sense Accuracy | ±14% Gm error at VREF = 0.5 V - impacts trip-point repeatability across temperature and supply variation |
| UVLO Threshold | 4.2 V (±0.25 V) rising - disables outputs until logic supply stabilizes, preventing erratic startup behavior |
Pinout & Package
Package: 28-pin TSSOP (suffix 'LP') with exposed thermal pad (pin 28). Power pins (VBB, GROUND, OUTA, OUTB) and thermal pad are at ground potential - no electrical isolation required. Lead-free, 100% matte tin leadframes.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 7, 8, 28 | GROUND | Common return for logic, power, and thermal pad - must be connected together at exposed pad for optimal thermal performance |
| 2, 3 | CP1, CP2 | Charge pump capacitor terminals - generate gate voltage > VBB for high-side DMOS drive |
| 4 | PHASE | Direction control input - sets OUTA/OUTB polarity (0 = OUTA low/OUTB high; 1 = OUTA high/OUTB low) |
| 5 | ROSC | Oscillator timing resistor - sets internal PWM frequency (fOSC ≈ 204×10⁹/ROSC) |
| 6 | VDD | Logic supply input (4.5–5.5 V) - powers internal logic, regulators, and gate drivers |
| 9 | ENABLE | PWM enable control - high enables selected bridge path; low initiates current decay per EXT MODE setting |
| 10, 12 | PFD2, PFD1 | Decay mode selection - configure slow (00), mixed (01/10), or fast (11) current decay during off-time |
| 13 | BLANK | Comparator blanking control - disables sense comparator for 6/fOSC (0) or 12/fOSC (1) after turn-on to reject switching transients |
| 14 | REF | Analog reference input (0–VDD) - sets current trip threshold via ITRIP = VREF/(10·RS) |
| 15 | EXT MODE | External PWM mode select - determines decay path when ENABLE is chopped (low = fast decay; high = slow decay) |
| 16 | OUTA | H-bridge output A - connects to one motor terminal; driven high/low depending on PHASE/ENABLE state |
| 18 | OUTB | H-bridge output B - connects to opposite motor terminal; complementary to OUTA in forward/reverse operation |
| 21 | SENSE | Current sense input - monitors voltage across external RS to detect ITRIP and trigger PWM off-time |
| 23 | SLEEP | Low-power mode control - logic low disables charge pump, regulator, and drivers to reduce quiescent current to 20 µA |
| 24 | VREG | Internal regulator output - supplies sink-side gate drive; requires 0.22 µF decoupling to ground |
| 25 | CP | Charge pump reservoir - connects to 0.22 µF capacitor between CP and VBB for high-side gate drive stability |
| 26 | LOAD SUPPLY | VBB input - high-current motor supply (9.5–50 V); decoupled with ≥47 µF electrolytic capacitor |
Key Features
| Feature | Design Value |
|---|---|
| Mixed/Fast/Slow Decay Modes | Selectable via PFD1/PFD2 to optimize torque ripple, acoustic noise, and braking response in varying load conditions |
| Synchronous Rectification | Reduces power dissipation by replacing body-diode conduction with low-rDS(on) DMOS paths during decay - eliminates need for external Schottky diodes |
| Internal Oscillator + ROSC Timing | Enables precise, stable PWM frequency control without external clock source - 4.25 MHz typical with 51 kΩ resistor |
| Zero-Current Detection | Disables all outputs when recirculating current reaches zero - prevents reverse current flow and improves control fidelity |
| Integrated Protection Suite | Includes thermal shutdown (165°C), UVLO (4.2 V), charge pump/VREG fault detection, and crossover-current prevention - no external supervision needed |
Applications
| Industrial Linear Actuators | Robotic Joint Controllers |
|---|---|
|
Use Scenario: Precise position control of electric linear actuators in factory automation, using PWM-modulated current to manage force and speed. IC Role / Device Role / Timing Role: Full-bridge driver executing bidirectional current control with real-time current limiting and decay-mode optimization. Use Value: ±3 A output and 270 mΩ rDS(on) enable high-force actuation while maintaining thermal stability on compact PCBs with 2-layer copper. |
Use Scenario: Torque-controlled joint movement in collaborative robots, requiring smooth reversal, low acoustic noise, and safe current limiting. IC Role / Device Role / Timing Role: Motor driver implementing mixed-decay mode (via PFD1/PFD2) to balance torque ripple and energy recovery during direction changes. Use Value: Synchronous rectification reduces heat generation by >40% vs. body-diode decay - critical for enclosed robotic joints with limited airflow. |
| Medical Infusion Pumps | Automated Door/Latch Systems |
|
Use Scenario: Constant-flow fluid delivery in battery-powered infusion pumps, demanding low quiescent current and reliable stall protection. IC Role / Device Role / Timing Role: Current-regulated H-bridge managing microstepped or analog-driven stepper/DC motors with sleep-mode power gating. Use Value: SLEEP input reduces standby current to 20 µA; thermal shutdown (165°C) and UVLO prevent unsafe operation during battery voltage sag. |
Use Scenario: Secure locking/unlocking of access doors using reversible DC motors, requiring fail-safe braking and EMI-optimized switching. IC Role / Device Role / Timing Role: Braking controller using slow-decay mode (EXT MODE = high) and ENABLE chopping to short motor BEMF without current sensing. Use Value: Internal crossover-current protection and 50 V VBB rating ensure robust operation across 12–24 V automotive-grade power rails. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar full-bridge PWM motor driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TB9051FTG | Integrated current-sense amplifier (no external RS required); higher 4.5 A rating; SPI interface for diagnostics | Requires microcontroller SPI support; better suited for closed-loop torque control than open-loop PWM setups | Choose TB9051FTG if system-level diagnostics, higher current headroom, or elimination of sense-resistor layout constraints are priorities |
| DRV8876N | Lower 3.6 A rating; integrated current regulation with adjustable decay; smaller 16-pin HTSSOP package | Lacks synchronous rectification; uses external diodes; lower thermal performance (RθJA = 52°C/W) | Choose DRV8876N only for space-constrained designs where 3 A margin is sufficient and thermal budget allows higher junction rise |
Compared with TB9051FTG and DRV8876N, the A3959SLP-T delivers superior thermal efficiency via synchronous rectification and offers deterministic decay-mode selection without MCU dependency - making it ideal for cost-sensitive, thermally constrained industrial motion systems requiring robust analog PWM control.
Availability
A3959SLP-T is available at Aetrix Electronics and suitable for industrial actuators, robotic joint controllers, medical infusion pumps, and automated door/latch systems requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for A3959SLP-T includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Allegro MicroSystems is a U.S.-based designer and manufacturer of high-performance magnetic sensors and power ICs, specializing in motion control, energy-efficient power conversion, and robust automotive-grade semiconductor solutions.
The A3959SLP-T belongs to Allegro's DMOS full-bridge motor driver product line, engineered specifically for industrial and medical motion systems requiring precise analog current regulation, thermal resilience, and minimal external component count.
FAQ
What is the maximum continuous output current supported by the A3959SLP-T?
The A3959SLP-T supports ±3 A continuous (repetitive) output current per channel, as specified in its Absolute Maximum Ratings table. This rating assumes proper PCB thermal design - for example, a 2-layer board with 1-in² copper area yields RθJA = 40°C/W, enabling full 3 A operation up to +85°C ambient. Peak current of ±6 A is allowed for pulses under 3 µs, but sustained operation above ±3 A risks thermal shutdown activation.
How does the A3959SLP-T implement current regulation without an external microcontroller?
The A3959SLP-T uses an internal fixed off-time PWM architecture that compares voltage across an external sense resistor (RS) to a scaled reference (VREF/10). When sensed current reaches ITRIP = VREF/(10·RS), the source driver turns off for a fixed 24 µs period. This analog feedback loop operates autonomously - no firmware, ADC, or digital control is required. The ROSC pin sets oscillator frequency, and PFD1/PFD2 configure decay behavior during the off-time.
Can the A3959SLP-T be used in braking applications, and how is braking implemented?
Yes, the A3959SLP-T supports active braking by configuring EXT MODE = high (slow-decay mode) and applying a chopped ENABLE signal. This shorts the motor terminals via both sink drivers during the off-cycle, dissipating kinetic energy as heat in the windings and MOSFETs. Note that braking current is not regulated by the internal current-sense circuit - it depends on back-EMF and winding resistance (IBRAKE ≈ VBEMF/RL), so worst-case mechanical conditions must be validated against the ±6 A peak rating.
What is the role of the SLEEP pin on the A3959SLP-T, and what power savings does it provide?
The SLEEP pin disables the internal charge pump, VREG regulator, and gate drivers when pulled low, reducing total supply current to ≤20 µA. This state preserves system-level power in battery-operated devices like portable medical pumps or remote actuators. When exiting sleep, the device resumes normal operation within microseconds - no power-up sequencing is required, and UVLO automatically re-enables drivers once VDD exceeds 4.2 V.
Does the A3959SLP-T require external Schottky diodes for flyback protection?
No, the A3959SLP-T eliminates the need for external Schottky diodes through integrated synchronous rectification. During current decay, the IC actively turns on appropriate DMOS pairs (e.g., both sinks in slow-decay mode) to provide a low-rDS(on) (270 mΩ) path for recirculating current - reducing conduction loss by ~60% compared to body-diode operation and lowering thermal stress on the IC and PCB.
A3959SLP-T Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Allegro MicroSystems
- Series:
- -
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width) Exposed Pad
- Packaging:
- Tube
- Product Status:
- Obsolete
- Motor Type - Stepper:
- -
- Motor Type - AC, DC:
- Brushed DC
- Function:
- Driver - Fully Integrated, Control and Power Stage
- Output Configuration:
- Half Bridge (2)
- Interface:
- Parallel
- Technology:
- DMOS
- Step Resolution:
- -
- Applications:
- General Purpose
- Current - Output:
- 3A
- Voltage - Supply:
- 4.5V ~ 5.5V
- Voltage - Load:
- 9.5V ~ 50V
- Operating Temperature:
- -20°C ~ 150°C (TJ)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 28-TSSOP-EP
A3959SLP-T FAQ
1.How can I place an order for A3959SLP-T through Aetrix?
Please submit a Request for Quotation (RFQ) for A3959SLP-T on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for A3959SLP-T reliable?
The price and inventory of A3959SLP-T are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for A3959SLP-T is usually 5 days.
3.What payment methods are accepted for A3959SLP-T?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for A3959SLP-T transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for A3959SLP-T?
A3959SLP-T orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your A3959SLP-T order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for A3959SLP-T?
For technical support, including A3959SLP-T datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your A3959SLP-T requirements.
6.How does Aetrix verify that A3959SLP-T is sourced from the original manufacturer or authorized distributors?
All A3959SLP-T products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that A3959SLP-T meets industry standards.
7.What is the process for return or replacement of A3959SLP-T?
All A3959SLP-T units undergo pre-shipment inspection (PSI). If there is an issue with A3959SLP-T, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The A3959SLP-T part is unused and in its original packaging.
Return procedure for A3959SLP-T:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
A3959SLP-T Tags
-
DRV2603RUNR
Texas Instruments

-
DRV8837CDSGR
Texas Instruments

-
DRV8837DSGR
Texas Instruments

-
DRV8838DSGR
Texas Instruments

-
DRV8839DSSR
Texas Instruments

-
EMC2301-1-ACZL-TR
Microchip Technology

-
DRV8231ADSGR
Texas Instruments

-
EMC2302-2-AIZL-TR
Microchip Technology

-
DRV8800PWPR
Texas Instruments

-
DRV8835DSSR
Texas Instruments

-
EMC2303-1-KP-TR
Microchip Technology

-
DRV8876PWPR
Texas Instruments
Tech Hub
A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.
TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

