NXP Semiconductors A3T21H400W23SR6

Overview

A3T21H400W23SR6 from NXP Semiconductors is a 71 W asymmetrical Doherty RF power LDMOS transistor designed for cellular base station amplifiers operating in the 2110–2200 MHz band. It features dual-gate architecture (Carrier and Peaking paths), 15.7 dB typical power gain at 2110 MHz, 52.8% drain efficiency, –29.2 dBc ACPR, and supports digital predistortion with 9.9 dB input PAR.

For engineers reviewing the A3T21H400W23SR6 datasheet, A3T21H400W23SR6 pinout, A3T21H400W23SR6 application, or A3T21H400W23SR6 equivalent, key selection criteria include its 28 V operation, 0.14 °C/W junction-to-case thermal resistance, 71 W average output power under W-CDMA, and validated 10:1 load mismatch tolerance at 32 Vdc.

Technical Context

The A3T21H400W23SR6 implements an internally matched asymmetrical Doherty architecture with separate Carrier (Pin 1/VGSA) and Peaking (Pin 2/VGSB) gate terminals, enabling independent bias control. Its dual-path design delivers wide instantaneous bandwidth across 2110–2200 MHz while maintaining <0.5 dB gain flatness at 71 W avg. output.

It operates with VDD supplied jointly to Pins 3 and 6, and RF outputs are isolated via DC-coupled Pins 4 (RFoutA/VDSA) and 5 (RFoutB/VDSB). The device supports Class C peaking operation via extended negative VGS range (–6.0 V) and withstands 436 W pulsed CW output at 10:1 VSWR without degradation.

Key Specifications

Pinout & Package

Package: ACP-1230S-4L2S - air-cavity plastic overmolded package with exposed thermal pad, 6-pin SMT layout optimized for high-power RF thermal management.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar RF power amplifier applications.

Compared with A3T21H400W23SR6, the R5 variant offers identical RF performance in smaller reels for validation, while AFM37D100W23SR6 provides higher power headroom at the cost of reduced gain and tighter thermal design constraints-neither is pin-compatible without layout review due to differing internal thermal vias and bond wire routing.

Availability

A3T21H400W23SR6 is available at Aetrix Electronics and suitable for macro cellular base stations, MIMO remote radio heads, and active antenna systems requiring stable component supply, high RF reliability, and long-term lifecycle support.

Supply support for A3T21H400W23SR6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and communications markets, with deep expertise in RF power technologies.

The A3T21H400W23SR6 belongs to NXP's AIRFAST® RF Power LDMOS family, engineered specifically for high-efficiency, broadband cellular infrastructure amplifiers operating in licensed sub-3 GHz bands.

FAQ

What is the maximum continuous drain voltage rating for the A3T21H400W23SR6?

The A3T21H400W23SR6 has a maximum drain-source voltage rating of +65 Vdc and a minimum of –0.5 Vdc, as specified in Table 1 of the official NXP datasheet (Rev. 0, June 2018). This rating applies under all operating conditions including transient events, and must not be exceeded during power-up, shutdown, or fault conditions. The A3T21H400W23SR6 is rated for 32 Vdc operating voltage, meaning system-level overvoltage protection must limit transients within the –0.5 to +65 Vdc window.

Can the A3T21H400W23SR6 operate with independent VDD supplies on Pins 3 and 6?

No-the A3T21H400W23SR6 requires VDDA and VDDB to be tied together and powered by a single DC source, as explicitly stated in the datasheet note on page 4. Using separate supplies risks current imbalance between internal drain paths, thermal hot-spotting, and premature failure. The A3T21H400W23SR6 is designed for symmetrical current sharing across both drain terminals when fed from one 28 Vdc rail with low-inductance decoupling.

What is the recommended gate bias sequence for safe turn-on of the A3T21H400W23SR6?

The A3T21H400W23SR6 requires VGSA (Pin 1) to be established before applying VDD, and VGSB (Pin 2) to be set after VDD stabilization. Per NXP application guidance, apply VGSA to 2.6 Vdc first, then ramp VDD to 28 Vdc, then set VGSB to 0.55 Vdc. This sequence prevents uncontrolled peaking device conduction and avoids excessive current surge. The A3T21H400W23SR6 datasheet specifies this three-step biasing to ensure reliable Doherty mode startup without latch-up.

Does the A3T21H400W23SR6 require external input/output matching components?

No-the A3T21H400W23SR6 is internally matched for 50 Ω operation across 2110–2200 MHz, as confirmed in Table 5 footnote and Figure 2 test circuit notes. External matching is unnecessary for fundamental-band operation; however, harmonic filtering remains required at RFoutA and RFoutB outputs per system spectral mask requirements. The A3T21H400W23SR6 achieves 15.7 dB gain and –29.2 dBc ACPR without external matching, simplifying front-end design.

What thermal interface material is recommended for mounting the A3T21H400W23SR6?

NXP recommends solder attach using SnAgCu (SAC305) reflow per AN1908, not thermal paste or epoxy. The A3T21H400W23SR6's ACP-1230S-4L2S package is qualified for direct solder attachment to copper heat spreaders or baseplates, achieving optimal 0.14 °C/W RθJC. Use of non-solder TIMs increases thermal resistance by ≥0.3 °C/W and voids NXP's reliability warranty. The A3T21H400W23SR6 must be mounted per JEDEC J-STD-020 moisture sensitivity level 3 guidelines.